US6028333A
Expired / Lapsed
US
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Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors
Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1996-07-19
•
Granted: 2000-02-22
•
Expires: 2016-07-19
Abstract
Abstract A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.
Inventors
- 👤 Shunpei Yamazaki
- 👤 Yasuhiko Takemura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6739; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3648; G09G3/3659; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; H10D86/00; H10D86/40; H10D86/60; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; G02F1/1333; G02F1/1345; G02F1/13454; G02F1/13624; G02F1/136245; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0823; G09G2330/00; G09G2330/08; H10D86/481
Claims Analysis
Total Claims: 70
Claim 1
Independent Claim
89 words
An electric device having a plurality of units arranged in a matrix, each of said plurality of units comprising: at least one p-channel type transistor having an active layer including source and drain regions, and a channel region therebetween; and at least one capacitor, wherein said at least one p-channel type transistor and said at least one capacitor are connected with one another in series, wherein an off current from said p-channel type transistor is less than 10 -12 A when a voltage of said drain region is 1V.
Claim 2
Dependent Claim
89 words
An electric device having a plurality of units arranged in a matrix, each of said plurality of units comprising: at least one p-channel type transistor having an active layer including source and drain regions, and a channel region therebetween; and at least one capacitor, wherein said at least one p-channel type transistor and said at least one capacitor are connected with one another in series, wherein an off current from said p-channel type transistor is less than 10 -12 A when a voltage of said drain region is 1V.
Claim 3
Dependent Claim
15 words
A device according to claim 1 wherein said electric device is a liquid crystal device.
Claim 4
Dependent Claim
14 words
A device according to claim 1 wherein said p-channel-type transistor is a multi-gate transistor.
Claim 5
Dependent Claim
170 words
An active matrix display device comprising: a plurality of data lines; a plurality of gate lines; a plurality of pixel electrodes; a plurality of p-channel type transistors, each of said p-channel type transistors being connected with corresponding one of said pixel electrodes through one of source and drain regions of said each of said p-channel type transistors and connected with corresponding one of said data lines through the other one of the source and drain regions and connected with corresponding one of said gate lines through a gate of said each of said p-channel type transistors wherein a side edge of a channel region of each of said p-channel type transistors extends beyond a side edge of a gate electrode of said each of said p-channel type transistors; and an electro-optical modulating layer provided between each of said pixel electrodes and a transparent conductive film, wherein an off current from each of said p-channel type transistors is less than 10 -12 A when a voltage of said drain is 1V.
Claim 6
Dependent Claim
170 words
An active matrix display device comprising: a plurality of data lines; a plurality of gate lines; a plurality of pixel electrodes; a plurality of p-channel type transistors, each of said p-channel type transistors being connected with corresponding one of said pixel electrodes through one of source and drain regions of said each of said p-channel type transistors and connected with corresponding one of said data lines through the other one of the source and drain regions and connected with corresponding one of said gate lines through a gate of said each of said p-channel type transistors wherein a side edge of a channel region of each of said p-channel type transistors extends beyond a side edge of a gate electrode of said each of said p-channel type transistors; and an electro-optical modulating layer provided between each of said pixel electrodes and a transparent conductive film, wherein an off current from each of said p-channel type transistors is less than 10 -12 A when a voltage of said drain is 1V.
Claim 7
Dependent Claim
34 words
A device according to claim 4 wherein a region provided between the source and drain regions in said p-type transistor contains a p-type impurity at a concentration of 10 17 atoms/cm 3 or less.
Claim 8
Dependent Claim
20 words
A device according to claim 4 wherein a region provided between the source and drain regions comprises a semi-amorphous semiconductor.
Claim 9
Dependent Claim
15 words
A device according to claim 4 wherein said p-type transistor serves as a switching means.
Claim 10
Dependent Claim
17 words
A device according to claim 2 wherein each of said p-channel type transistors is a multi-gate transistor.
Claim 11
Dependent Claim
107 words
An electric device having a plurality of units arranged in a matrix and having a plurality of complementary transistor pairs provided around said plurality of units arranged in the matrix, each of said plurality of units comprising: at least one p-channel type transistor having an active layer including source and drain regions, and a channel region therebetween; and at least one capacitor, wherein said at least one p-channel type transistor and said at least one capacitor are connected with one another in series, wherein an off current from said p-channel type transistor is less than 10 -12 A when a voltage of said drain region is 1V.
Claim 12
Dependent Claim
107 words
An electric device having a plurality of units arranged in a matrix and having a plurality of complementary transistor pairs provided around said plurality of units arranged in the matrix, each of said plurality of units comprising: at least one p-channel type transistor having an active layer including source and drain regions, and a channel region therebetween; and at least one capacitor, wherein said at least one p-channel type transistor and said at least one capacitor are connected with one another in series, wherein an off current from said p-channel type transistor is less than 10 -12 A when a voltage of said drain region is 1V.
Claim 13
Dependent Claim
37 words
A device according to claim 9 wherein at least one of said complementary transistor pairs comprises a gate electrode and an oxide of a material of said gate electrode provided on a surface of said gate electrode.
Claim 14
Dependent Claim
63 words
A device according to claim 9 further comprising at least one n-channel type transistor wherein each of said at least one n-channel type transistor is connected with corresponding p-channel type transistor in series and one of source and drain of each of said at least one n-channel type transistor is connected with one of source and drain of the corresponding p-channel type transistor.
Claim 15
Dependent Claim
15 words
A device according to claim 9 wherein said p-channel type transistor is a multi-gate transistor.
Claim 16
Dependent Claim
73 words
An electric device having a plurality of thin film transistors arranged in a matrix form, each of said thin film transistors being p-channel type and comprising: a semiconductor film formed on an insulating surface; a gate insulating film adjacent to said semiconductor film; and a gate electrode adjacent to said gate insulating film, wherein an off current of one of said thin film transistors is 10 -12 A when a drain voltage 1V.
Claim 17
Dependent Claim
73 words
An electric device having a plurality of thin film transistors arranged in a matrix form, each of said thin film transistors being p-channel type and comprising: a semiconductor film formed on an insulating surface; a gate insulating film adjacent to said semiconductor film; and a gate electrode adjacent to said gate insulating film, wherein an off current of one of said thin film transistors is 10 -12 A when a drain voltage 1V.
Claim 18
Dependent Claim
17 words
A device according to claim 13 wherein each of said p-channel type transistors is a multi-gate transistor.
Claim 19
Dependent Claim
142 words
An electric device comprising: a plurality of pixel electrodes provided on a substrate; and a plurality of p-channel type transistors provided on said substrate, each of said p-channel type transistors being connected with corresponding one of said pixel electrodes at one of source and drain of said each of said p-channel type transistors; wherein a region provided between said source and said drain comprises a first layer comprising a semiconductor selected from the group consisting of a single crystalline semiconductor, a polycrystal semiconductor and a semi-amorphous semiconductor, and a second layer provided under said first layer and comprising an amorphous semiconductor of the same material as said first layer, and wherein a side edge of a channel region of each of said p-channel type transistors extends beyond a side edge of a gate electrode of said each of said p-channel type transistors.
Claim 20
Dependent Claim
142 words
An electric device comprising: a plurality of pixel electrodes provided on a substrate; and a plurality of p-channel type transistors provided on said substrate, each of said p-channel type transistors being connected with corresponding one of said pixel electrodes at one of source and drain of said each of said p-channel type transistors; wherein a region provided between said source and said drain comprises a first layer comprising a semiconductor selected from the group consisting of a single crystalline semiconductor, a polycrystal semiconductor and a semi-amorphous semiconductor, and a second layer provided under said first layer and comprising an amorphous semiconductor of the same material as said first layer, and wherein a side edge of a channel region of each of said p-channel type transistors extends beyond a side edge of a gate electrode of said each of said p-channel type transistors.
Claim 21
Dependent Claim
17 words
A device according to claim 15 wherein each of said p-channel type transistors is a multi-gate transistor.
Claim 22
Dependent Claim
149 words
An electric device comprising: a substrate; a buffer layer formed on said substrate; a plurality of pixel electrodes provided on said buffer layer, each of said pixel electrodes being provided with at least one pixel transistor; an electro-optical modulating layer located adjacent to said pixel electrodes; and a peripheral circuit formed on a peripheral portion of said substrate for driving said pixel transistor, wherein said at least one pixel transistor is at least one thin film transistor having only p-channel type and having an active layer including source and drain regions and a channel region therebetween, and wherein a side edge of said channel region of said at least one thin film transistor extends beyond a side edge of a gate electrode of said transistor, wherein an off current from said thin film transistor is less than 10 -12 A when a voltage of said drain region is 1V.
Claim 23
Dependent Claim
149 words
An electric device comprising: a substrate; a buffer layer formed on said substrate; a plurality of pixel electrodes provided on said buffer layer, each of said pixel electrodes being provided with at least one pixel transistor; an electro-optical modulating layer located adjacent to said pixel electrodes; and a peripheral circuit formed on a peripheral portion of said substrate for driving said pixel transistor, wherein said at least one pixel transistor is at least one thin film transistor having only p-channel type and having an active layer including source and drain regions and a channel region therebetween, and wherein a side edge of said channel region of said at least one thin film transistor extends beyond a side edge of a gate electrode of said transistor, wherein an off current from said thin film transistor is less than 10 -12 A when a voltage of said drain region is 1V.
Claim 24
Dependent Claim
16 words
A device according to claim 17 wherein said peripheral circuit comprises thin film type CMOS circuits.
Claim 25
Dependent Claim
24 words
A device according to claim 17 further comprising a capacitor connected to said p-channel type thin film transistor in series at respective pixel electrodes.
Claim 26
Dependent Claim
34 words
A device according to claim 17 wherein said p-channel type thin film transistor has a channel semiconductor layer in which a concentration of p-type impurity is not higher than 10 17 atoms/cm 3 .
Claim 27
Dependent Claim
22 words
A device according to claim 17 wherein said peripheral circuit includes an inventor circuit formed with a complementary thin film transistor pair.
Claim 28
Dependent Claim
18 words
A device according to claim 17 wherein said peripheral circuit comprises a transmission gate formed of complementary transistors.
Claim 29
Dependent Claim
14 words
A device according to claim 17 wherein said pixel transistor is a multi-gate transistor.
Claim 30
Dependent Claim
70 words
An electric device comprising: a substrate; a plurality of pixel electrodes provided over said substrate, each of said pixel electrodes being provided with at least two p-channel type thin film transistors connected in series; and an electro-optical modulating layer located adjacent to said substrate; wherein an off current of each of said two p-channel type thin film transistors is less than 10 -12 A when a drain voltage is 1V.
Claim 31
Dependent Claim
70 words
An electric device comprising: a substrate; a plurality of pixel electrodes provided over said substrate, each of said pixel electrodes being provided with at least two p-channel type thin film transistors connected in series; and an electro-optical modulating layer located adjacent to said substrate; wherein an off current of each of said two p-channel type thin film transistors is less than 10 -12 A when a drain voltage is 1V.
Claim 32
Dependent Claim
46 words
A device according to claim 24 wherein each of said two p-channel type thin film transistors has a gate electrode, and said gate electrode is offset from at least one of a source and a drain of each of said two p-channel type thin film transistors.
Claim 33
Dependent Claim
14 words
A device according to claim 24 wherein said pixel transistor is a multi-gate transistor.
Claim 34
Dependent Claim
97 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided over said substrate; an electro-optical modulating layer located adjacent to said pixel electrodes; and a plurality of thin film transistors formed over said substrate and electrically connected with said plurality of pixel electrodes, each of said thin film transistors including a channel region comprising silicon, wherein an off current from said thin film transistor is less than 10 -12 A when a drain voltage is 1V, and wherein said channel region comprises boron at a concentration less than 10 17 cm -3 .
Claim 35
Dependent Claim
97 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided over said substrate; an electro-optical modulating layer located adjacent to said pixel electrodes; and a plurality of thin film transistors formed over said substrate and electrically connected with said plurality of pixel electrodes, each of said thin film transistors including a channel region comprising silicon, wherein an off current from said thin film transistor is less than 10 -12 A when a drain voltage is 1V, and wherein said channel region comprises boron at a concentration less than 10 17 cm -3 .
Claim 36
Dependent Claim
16 words
A device according to claim 27 wherein said peripheral circuit comprises thin film type CMOS circuits.
Claim 37
Dependent Claim
23 words
A device according to claim 27 further comprising a capacitor connected to said p-channel type thin transistor in series at respective pixel electrodes.
Claim 38
Dependent Claim
14 words
A device according to claim 27 wherein said pixel transistor is a multi-gate transistor.
Claim 39
Dependent Claim
154 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided on said substrate, each of said pixel electrodes being provided with a switching element; an electro-optical modulating layer located adjacent to said pixel electrodes; and a peripheral circuit formed on a peripheral portion of said substrate for driving said pixel transistor, wherein said switching element comprises only at least two p-channel type thin film transistors being connected in series with respect to said pixel electrode, each of said thin film transistors having an active layer including source and drain regions, and a channel region therebetween, wherein an off current from each of said p-channel type thin film transistors is less than 10 -12 A when a voltage of said drain region is 1V, wherein said channel region of said two p-channel thin film transistors comprises and an amorphous silicon layer and a crystalline silicon layer on said amorphous silicon layer.
Claim 40
Dependent Claim
154 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided on said substrate, each of said pixel electrodes being provided with a switching element; an electro-optical modulating layer located adjacent to said pixel electrodes; and a peripheral circuit formed on a peripheral portion of said substrate for driving said pixel transistor, wherein said switching element comprises only at least two p-channel type thin film transistors being connected in series with respect to said pixel electrode, each of said thin film transistors having an active layer including source and drain regions, and a channel region therebetween, wherein an off current from each of said p-channel type thin film transistors is less than 10 -12 A when a voltage of said drain region is 1V, wherein said channel region of said two p-channel thin film transistors comprises and an amorphous silicon layer and a crystalline silicon layer on said amorphous silicon layer.
Claim 41
Dependent Claim
30 words
A device according to claim 31 wherein said at least two p-channel type thin film transistors are inserted in series with a data line and with the corresponding pixel electrode.
Claim 42
Dependent Claim
16 words
A device according to claim 31 wherein said peripheral circuit comprises thin film type CMOS circuits.
Claim 43
Dependent Claim
21 words
A device according to claim 31 further comprising a capacitor connected to said switching element in series at respective pixel electrodes.
Claim 44
Dependent Claim
109 words
An electro-optical display device comprising: a substrate having an insulating surface; and a plurality of pixel electrodes provided on said insulating surface, each of said pixel electrodes being provided with one or a plurality of MOS transistors which have only one conductivity type, each of said MOS transistors having at least a channel semiconductor region and source and drain semiconductor regions wherein a side edge of said channel semiconductor region extends beyond a side edge of a gate electrode, and said source and drain semiconductor regions having a p-type conductivity, wherein said channel semiconductor region comprises a laminar structure comprising an amorphous silicon layer and a crystalline silicon layer.
Claim 45
Dependent Claim
109 words
An electro-optical display device comprising: a substrate having an insulating surface; and a plurality of pixel electrodes provided on said insulating surface, each of said pixel electrodes being provided with one or a plurality of MOS transistors which have only one conductivity type, each of said MOS transistors having at least a channel semiconductor region and source and drain semiconductor regions wherein a side edge of said channel semiconductor region extends beyond a side edge of a gate electrode, and said source and drain semiconductor regions having a p-type conductivity, wherein said channel semiconductor region comprises a laminar structure comprising an amorphous silicon layer and a crystalline silicon layer.
Claim 46
Dependent Claim
22 words
A device according to claim 35 wherein said source and drain semiconductor regions have a higher crystallinity than said channel semiconductor region.
Claim 47
Dependent Claim
17 words
A device according to claim 35 wherein said channel semiconductor region has an N - type conductivity.
Claim 48
Dependent Claim
26 words
A device according to claim 35 wherein said channel semiconductor region and said source and drain semiconductor regions are formed within one semiconductor film comprising silicon.
Claim 49
Dependent Claim
16 words
A device according to claim 35 wherein each of said MOS transistors is a multi-gate transistor.
Claim 50
Dependent Claim
119 words
An active matrix display device comprising: a substrate having an insulating surface; and a plurality of pixel electrodes provided on said insulating surface, each of said pixel electrodes being provided with at least one MOS transistor having only one conductivity type and comprising at least a channel region and source and drain regions said source and drain regions having a p-type conductivity, wherein said channel region is thinner than said source and drain regions, wherein an off current from said MOS transistors is less than 10 -12 A when a voltage of said drain region is 1V, wherein said channel region of MOS transistor comprises an amorphous silicon layer and a crystalline silicon layer on said amorphous silicon layer.
Claim 51
Dependent Claim
119 words
An active matrix display device comprising: a substrate having an insulating surface; and a plurality of pixel electrodes provided on said insulating surface, each of said pixel electrodes being provided with at least one MOS transistor having only one conductivity type and comprising at least a channel region and source and drain regions said source and drain regions having a p-type conductivity, wherein said channel region is thinner than said source and drain regions, wherein an off current from said MOS transistors is less than 10 -12 A when a voltage of said drain region is 1V, wherein said channel region of MOS transistor comprises an amorphous silicon layer and a crystalline silicon layer on said amorphous silicon layer.
Claim 52
Dependent Claim
16 words
A device according to claim 40 wherein said channel region has a N - type conductivity.
Claim 53
Dependent Claim
21 words
A device according to claim 40 further comprising another pMOS transistor connected to said at least one MOS transistor in series.
Claim 54
Dependent Claim
24 words
A device according to claim 40 wherein said channel region and said source and drain regions are formed within one semiconductor film comprising silicon.
Claim 55
Dependent Claim
14 words
A device according to claim 40 wherein said MOS transistor is a multi-gate transistor.
Claim 56
Dependent Claim
89 words
An active matrix display device comprising: a plurality of p-channel transistors formed in a matrix on an insulating surface, each of said p-channel transistors having an active layer including source and drain regions, and a channel region therebetween, wherein an off current from each of said p-channel transistors is less than 10 -12 A wherein a voltage of said drain region is 1V, wherein said channel region of each of said thin film transistors comprises an amorphous silicon layer and a crystalline silicon layer on said amorphous silicon layer.
Claim 57
Dependent Claim
89 words
An active matrix display device comprising: a plurality of p-channel transistors formed in a matrix on an insulating surface, each of said p-channel transistors having an active layer including source and drain regions, and a channel region therebetween, wherein an off current from each of said p-channel transistors is less than 10 -12 A wherein a voltage of said drain region is 1V, wherein said channel region of each of said thin film transistors comprises an amorphous silicon layer and a crystalline silicon layer on said amorphous silicon layer.
Claim 58
Dependent Claim
16 words
A device according to claim 45 wherein each of said p-channel transistors is a multi-gate transistor.
Claim 59
Dependent Claim
134 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided over said substrate; a plurality of thin film transistors formed over said substrate and electrically connected with said plurality of pixel electrodes, each of said thin film transistors including: a silicon nitride film formed on the substrate, a silicon oxide film formed on the substrate, a silicon film formed on the silicon oxide film, said silicon film including source and drain regions, and a channel region interposed therebetween, a gate electrode formed adjacent to the channel region with a gate insulating therebetween, wherein an off current from said thin film transistor is less than 10 -12 A wherein a drain voltage is 1V, and wherein said channel region comprises boron at a concentration less than 10 17 cm -3 .
Claim 60
Dependent Claim
134 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided over said substrate; a plurality of thin film transistors formed over said substrate and electrically connected with said plurality of pixel electrodes, each of said thin film transistors including: a silicon nitride film formed on the substrate, a silicon oxide film formed on the substrate, a silicon film formed on the silicon oxide film, said silicon film including source and drain regions, and a channel region interposed therebetween, a gate electrode formed adjacent to the channel region with a gate insulating therebetween, wherein an off current from said thin film transistor is less than 10 -12 A wherein a drain voltage is 1V, and wherein said channel region comprises boron at a concentration less than 10 17 cm -3 .
Claim 61
Dependent Claim
19 words
A device according to claim 47, wherein each of the plurality of thin film transistors is a top-gate transistor.
Claim 62
Dependent Claim
17 words
A device according to claim 47, wherein said silicon film comprises polycrystalline silicon or single crystal silicon.
Claim 63
Dependent Claim
90 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided over said substrate; a plurality of multi-gate type thin film transistors formed over said substrate and electrically connected with said plurality of pixel electrodes, each of said thin film transistors including a channel region comprising silicon, wherein an off current from said thin film transistor is less than 10 -12 A wherein a drain voltage is 1V, and wherein said channel region comprises a p-type impurity at a concentration less than 10 17 cm -3 .
Claim 64
Dependent Claim
90 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided over said substrate; a plurality of multi-gate type thin film transistors formed over said substrate and electrically connected with said plurality of pixel electrodes, each of said thin film transistors including a channel region comprising silicon, wherein an off current from said thin film transistor is less than 10 -12 A wherein a drain voltage is 1V, and wherein said channel region comprises a p-type impurity at a concentration less than 10 17 cm -3 .
Claim 65
Dependent Claim
21 words
A device according to claim 50, wherein each of the plurality of multi-gate type thin film transistors is a top-gate transistor.
Claim 66
Dependent Claim
17 words
A device according to claim 50, wherein said channel region comprises polycrystalline silicon or single crystal silicon.
Claim 67
Dependent Claim
136 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided over said substrate; a plurality of thin film transistors formed over said substrate and electrically connected with said plurality of pixel electrodes, each of said thin film transistors including: a silicon nitride film formed on the substrate, a silicon oxide film formed on the substrate, a silicon film formed on the silicon oxide film, said silicon film including source and drain regions, and a channel region interposed therebetween, a gate electrode formed adjacent to the channel region with a gate insulating therebetween, wherein an off current from said thin film transistor is less than 10 -12 A wherein a drain voltage is 1V, and wherein said channel region comprises a p-type impurity at a concentration less than 10 17 cm -3 .
Claim 68
Dependent Claim
136 words
An active matrix display device comprising: a substrate; a plurality of pixel electrodes provided over said substrate; a plurality of thin film transistors formed over said substrate and electrically connected with said plurality of pixel electrodes, each of said thin film transistors including: a silicon nitride film formed on the substrate, a silicon oxide film formed on the substrate, a silicon film formed on the silicon oxide film, said silicon film including source and drain regions, and a channel region interposed therebetween, a gate electrode formed adjacent to the channel region with a gate insulating therebetween, wherein an off current from said thin film transistor is less than 10 -12 A wherein a drain voltage is 1V, and wherein said channel region comprises a p-type impurity at a concentration less than 10 17 cm -3 .
Claim 69
Dependent Claim
19 words
A device according to claim 53, wherein each of the plurality of thin film transistors is a top-gate transistor.
Claim 70
Dependent Claim
17 words
A device according to claim 53, wherein said silicon film comprises polycrystalline silicon or single crystal silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-21 | 2003-08-23 | 2004-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-21 | 2007-08-23 | 2008-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-21 | 2011-08-23 | 2012-02-22 | $7700.00 | Window Closed / Lapsed |