US4762807A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making a non-single crystal insulated-gate field effect transistor
Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1986-08-13
•
Granted: 1988-08-09
•
Expires: 2006-08-13
Abstract
Abstract An insulated-gate field effect transistor (IGFET) having the structure of the source and drain disposed in the longitudinal direction, i.e., the laminating direction, so that the channel region extends in the lateral direction when a high voltage is applied. This structure prevents a high current density at the interface of the channel region and the gate insulation film, allowing the fabrication of a large-current power transistor or the integration of such transistors.
Inventors
- 👤 Shunpei Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; H10D30/67; H10D30/6704; H10D30/6728; H10D30/674; H10D30/6741; H10D62/00; H10D62/40; H10D62/80; H10D62/82; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/693; Y; Y10; Y10S; Y10S148/00; Y10S148/122; Y10S148/148
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
227 words
A method of fabricating an insulated-gate field effect semiconductor device comprising the steps of: forming a first non-single-crystal silicon semiconductor layer (3) having one conductivity type on a substrate or a conductive layer on said substrate, and a second non-single-crystal silicon semiconductor layer (4) of an intrinsic or virtually intrinsic conductivity type on said first semiconductor layer (3) by use of a chemical vapor deposition method; forming a third non-single-crystal silicon semiconductor layer (5) of the same conductivity type as that of said first non-single-crystal silicon semiconductor layer (3) on said second non-single-crystal silicon semiconductor layer (4) by the chemical vapor deposition method; removing a portion of said third non-single-crystal silicon semiconductor layer so that a protuberant portion of the third non-single-crystal silicon semiconductor layer remains on said second non-single-crystal silicon semiconductor layer, said protuberant portion having at least one side surface; forming a fourth non-single-crystal silicon semiconductor layer (7) of an intrinsic or virtually intrinsic conductivity type on at least the side surface of said protuberant portion of said third non-single-crystal silicon semiconductor layer (5) and on an upper surface of said second semiconductor layer (4); forming a gate insulation film (8) on said fourth non-single-crystal silicon semiconductor layer (7); and forming a gate electrode on said gate insulation film (8), where said second non-single-crystal silicon semiconductor layer is formed of Si x C 1-x (0<x<1).
Claim 2
Independent Claim
227 words
A method of fabricating an insulated-gate field effect semiconductor device comprising the steps of: forming a first non-single-crystal silicon semiconductor layer (3) having one conductivity type on a substrate or a conductive layer on said substrate, and a second non-single-crystal silicon semiconductor layer (4) of an intrinsic or virtually intrinsic conductivity type on said first semiconductor layer (3) by use of a chemical vapor deposition method; forming a third non-single-crystal silicon semiconductor layer (5) of the same conductivity type as that of said first non-single-crystal silicon semiconductor layer (3) on said second non-single-crystal silicon semiconductor layer (4) by the chemical vapor deposition method; removing a portion of said third non-single-crystal silicon semiconductor layer so that a protuberant portion of the third non-single-crystal silicon semiconductor layer remains on said second non-single-crystal silicon semiconductor layer, said protuberant portion having at least one side surface; forming a fourth non-single-crystal silicon semiconductor layer (7) of an intrinsic or virtually intrinsic conductivity type on at least the side surface of said protuberant portion of said third non-single-crystal silicon semiconductor layer (5) and on an upper surface of said second semiconductor layer (4); forming a gate insulation film (8) on said fourth non-single-crystal silicon semiconductor layer (7); and forming a gate electrode on said gate insulation film (8), where said second non-single-crystal silicon semiconductor layer is formed of Si x C 1-x (0<x<1).
Claim 3
Dependent Claim
8 words
A method as in claim 1 where 0.8≦x≦0.9.
References Cited (Backward Citations)
US4332075A
Cited
US4364167A
Cited
US4470060A
Cited
US4633287A
Cited
US4543320A
Cited
US4547789A
Cited
US4620208A
Cited
US4633284A
Cited
US4568958A
Cited
US4673957A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |