US4942441A
Expired / Lapsed
US
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Thin film semiconductor device and method of manufacturing the same
Assignee: Hitachi Ltd
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Filing: 1987-03-27
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Granted: 1990-07-17
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Expires: 2007-03-27
Abstract
Abstract Complementary thin fillm transistors (C-TFT) formed on an insulating substrate, comprising a pair of highly resistive n-type silicon islands, a pair of heavily doped n-type regions formed in one of the islands to form source and drain regions of n-channel TFT, a pair of contacts formed on the surface of the other island and establishing a high potential barrier when the underlying region is of n-type and a low potential barrier when the underlying region is inverted to be of p-type. The process for manufacturing complementary TFTs can be simplified significantly.
Inventors
- 👤 Nobutake Konishi
- 👤 Yoshikazu Hosokawa
- 👤 Akio Mimura
- 👤 Takaya Suzuki
- 👤 Jun-ichi Ohwada
- 👤 Hideaki Kawakami
- 👤 Kenji Miyata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:34
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/40; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D64/00; H10D64/60; H10D64/64; H10D64/647; H10D86/01; H10D86/021; H10D86/60; G02F2202/00; G02F2202/10; G02F2202/103; G02F2202/104
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
268 words
A complementary thin film semiconductor device comprising: an insulating underlie for supporting the semiconductor device to be formed thereon; a pair of thin film semiconductor island regions supported on said insulating underlie, spaced from each other and having a high resistivity and a conductivity type of i- or n-type; a pair of heavily doped n-type regions formed on one of said island regions and spaced from each other by a predetermined distance, the heavily doped regions constituting a source and a drain region of an n-channel thin film transistor (n-TFT) and the predetermined distance defining a channel length of the n-TFT; a first pair of metal contacts formed on a surface of the other of said island regions and spaced from each other by another predetermined distance, the metal contact forming a high potential barrier when the underlying semiconductor region is of n-type and a reduced potential barrier when the underlying region is of p-type, the pair of metal contacts constituting a source and a drain region of a p-channel thin film transistor (p-TFT) and said another predetermined distance defining a channel length of the p-TFT; a pair of insulated gate structures formed on said pair of island regions, each at a position between the source and the drain of the associated TFT; and a second pair of metal contacts formed on said pair of heavily doped n-type regions not to contact directly with said island region, wherein the insulated gate structure of the n-channel thin film transistor is formed to overlap predetermined portions of said source region and said drain region of the n-channel thin film transistor.
Claim 2
Dependent Claim
268 words
A complementary thin film semiconductor device comprising: an insulating underlie for supporting the semiconductor device to be formed thereon; a pair of thin film semiconductor island regions supported on said insulating underlie, spaced from each other and having a high resistivity and a conductivity type of i- or n-type; a pair of heavily doped n-type regions formed on one of said island regions and spaced from each other by a predetermined distance, the heavily doped regions constituting a source and a drain region of an n-channel thin film transistor (n-TFT) and the predetermined distance defining a channel length of the n-TFT; a first pair of metal contacts formed on a surface of the other of said island regions and spaced from each other by another predetermined distance, the metal contact forming a high potential barrier when the underlying semiconductor region is of n-type and a reduced potential barrier when the underlying region is of p-type, the pair of metal contacts constituting a source and a drain region of a p-channel thin film transistor (p-TFT) and said another predetermined distance defining a channel length of the p-TFT; a pair of insulated gate structures formed on said pair of island regions, each at a position between the source and the drain of the associated TFT; and a second pair of metal contacts formed on said pair of heavily doped n-type regions not to contact directly with said island region, wherein the insulated gate structure of the n-channel thin film transistor is formed to overlap predetermined portions of said source region and said drain region of the n-channel thin film transistor.
Claim 3
Dependent Claim
48 words
A complementary thin film semiconductor device according to claim 1, wherein said semiconductor is silicon of polycrystalline, micro-crystalline or amorphous state, and said metal contact is formed of one selected from the group consisting of Ti, Ta, Cr, Mo, Pd, Pt, W, their silicides and the mixtures thereof.
Claim 4
Dependent Claim
32 words
A complementary thin film semiconductor device according to claim 1, wherein said insulated gate structure and said source and drain regions are all disposed on a same side of the island region.
Claim 5
Dependent Claim
41 words
A complementary thin film semiconductor device according to claim 1, wherein said insulated gate structure is disposed between said insulating underlie and said island region, and said source and drain regions are disposed on the other side of the island region.
Claim 6
Dependent Claim
24 words
A complementary thin film semiconductor device according to claim 1, further comprising a conductive wiring pattern connecting the source regions of n-TFT and p-TFT.
Claim 7
Dependent Claim
32 words
A complementary thin film semiconductor device according to claim 5, further comprising another conductive wiring pattern connecting an input signal line with said insulated gate structures, thereby forming a complementary TFT inverter.
Claim 8
Dependent Claim
21 words
A complementary thin film semiconductor device according to claim 1, wherein said insulating underlie is a transparent substrate carrying transparent electrodes.
Claim 9
Dependent Claim
21 words
A complementary thin film semiconductor device according to claim 7, further comprising a liquid crystal display associated with said transparent electrodes.
Claim 10
Dependent Claim
22 words
A complementary thin film semiconductor device according to claim 8, wherein said TFTs constitute a circuit for driving said liquid crystal display.
Claim 11
Dependent Claim
33 words
A complementary thin film semiconductor device according to claim 1, wherein said second pair of metal contacts are formed substantially of the same material as that of said first pair of metal contacts.
Claim 12
Dependent Claim
22 words
A complementary thin film semiconductor device according to claim 1, wherein said first and second pairs of metal contacts are metal silicide.
Claim 13
Dependent Claim
22 words
A complementary thin film semiconductor device according to claim 10, wherein said first and second pairs of metal contacts are metal silicide.
Claim 14
Dependent Claim
237 words
A complementary thin film semiconductor device comprising: an insulating underlie for supporting the semiconductor device ot be formed thereon; a pair of thin film semiconductor island regions supported on said insulating underlie, sapced from each other and having a high resistivity and a conductivity type of i- or n-type; a pair of heavily doped n-type regions formed on one of said island regions and spaced from each other by a predetermined distance, the heavily doped regions constituting a source and a drain region of an n-channel thin film transistor (n-TFT) and the predetermined distance defining a channel length of the n-TFT; a first pair of metal contacts formed on a surface of the other of said island regions and spaced from each other by another predetermined distance, the metal contact forming a high potential barrier when teh underlying semiconductor region is of n-type and a reduced potential barrier when the underlying region is of p-type, the pair of metal contacts constituting a source and a drain region of a p-channel thin film transistor (p-TFT) and said another predetermined distance defining a channel length of the p-TFT; and a pair of insulated gate structures formed on said pair of island regions, each at a position between the source and the drain of the asosciated TFT, wherein the insulated gate structure n-TFT is formed to overlap predetermined portions of said source region and said drain region of the n-TFT.
Claim 15
Dependent Claim
237 words
A complementary thin film semiconductor device comprising: an insulating underlie for supporting the semiconductor device ot be formed thereon; a pair of thin film semiconductor island regions supported on said insulating underlie, sapced from each other and having a high resistivity and a conductivity type of i- or n-type; a pair of heavily doped n-type regions formed on one of said island regions and spaced from each other by a predetermined distance, the heavily doped regions constituting a source and a drain region of an n-channel thin film transistor (n-TFT) and the predetermined distance defining a channel length of the n-TFT; a first pair of metal contacts formed on a surface of the other of said island regions and spaced from each other by another predetermined distance, the metal contact forming a high potential barrier when teh underlying semiconductor region is of n-type and a reduced potential barrier when the underlying region is of p-type, the pair of metal contacts constituting a source and a drain region of a p-channel thin film transistor (p-TFT) and said another predetermined distance defining a channel length of the p-TFT; and a pair of insulated gate structures formed on said pair of island regions, each at a position between the source and the drain of the asosciated TFT, wherein the insulated gate structure n-TFT is formed to overlap predetermined portions of said source region and said drain region of the n-TFT.
References Cited (Backward Citations)
US4091527A
Cited
US4206472A
Cited
US4300152A
Cited
JPS58223362A
Cited
US4736229A
Cited
JPS6074561A
Cited
JPS60154661A
Cited
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