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US6026465A
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Flash memory including a mode register for indicating synchronous or asynchronous mode of operation
Assignee: Intel Corp
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Filing: 1997-06-18
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Granted: 2000-02-15
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Expires: 2017-06-18
Abstract
Abstract A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip. In the third read mode, asynchronous DRAM mode, the row and column addresses are strobed into the flash memory using strobe signals. The flash memory then converts the row and column addresses internally into a single address and provides as output the data stored at that single address. The flash memory does not need an extended precharge period or to be refreshed, but can be controlled by a standard DRAM controller. In the fourth read mode, synchronous DRAM mode, the flash memory emulates a synchronous DRAM.
Inventors
- 👤 Duane R. Mills
- 👤 Brian Lyn Dipert
- 👤 Sachidanandan Sambandan
- 👤 Bruce McCormick
- 👤 Richard D. Pashley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:57
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/06; G06F12/0607; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045; G11C7/1072; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
141 words
A nonvolatile memory apparatus comprising: a first bank of nonvolatile memory; a second bank of nonvolatile memory, wherein consecutive addresses of the nonvolatile memory apparatus are interlaced between the first and second banks; interlace control logic for receiving address signals, asynchronous control signals, and synchronous control signals including a clock signal; and a mode register, wherein the interface control logic provides synchronous access to the first and second memory banks in accordance with the address signals and synchronous control signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing a first value, wherein the interface control logic provides asynchronous access to the first and second memory banks independent of the clock signal in accordance with the address signals and asynchronous control signals if the mode register is storing a second value.
Claim 2
Dependent Claim
141 words
A nonvolatile memory apparatus comprising: a first bank of nonvolatile memory; a second bank of nonvolatile memory, wherein consecutive addresses of the nonvolatile memory apparatus are interlaced between the first and second banks; interlace control logic for receiving address signals, asynchronous control signals, and synchronous control signals including a clock signal; and a mode register, wherein the interface control logic provides synchronous access to the first and second memory banks in accordance with the address signals and synchronous control signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing a first value, wherein the interface control logic provides asynchronous access to the first and second memory banks independent of the clock signal in accordance with the address signals and asynchronous control signals if the mode register is storing a second value.
Claim 3
Dependent Claim
28 words
The nonvolatile memory apparatus of claim 1 wherein the first and second nonvolatile memory banks, interlace control logic, and mode register are formed within a same integrated circuit.
Claim 4
Dependent Claim
16 words
The nonvolatile memory of claim 1 wherein the mode register is implemented with content addressable memory.
Claim 5
Dependent Claim
14 words
The nonvolatile memory of claim 1 wherein the nonvolatile memory is a flash memory.
Claim 6
Dependent Claim
173 words
The nonvolatile memory apparatus of claim 1 further comprising: a first address latch coupled to provide at least a portion of the received address signals to the first bank in accordance with an address latch enable signal of the synchronous control signals; a second address latch coupled to provide the portion of the received address signals to the second bank in accordance with the address latch enable signal; wherein the interface control logic provides the address latch enable signal to a selected one of the first and second address latches in accordance with at least one bit of the address signals if the mode register is storing the first value; and a data multiplexer coupled to the first and second banks of nonvolatile memory, wherein the data multiplexer synchronously selects data from one of the first and second banks in accordance with the at least one bit and the clock signal to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing the first value.
Claim 7
Dependent Claim
36 words
The nonvolatile memory apparatus of claim 5 wherein the first and second banks of nonvolatile memory, interlace control logic, mode register, first and second address latches, and data multiplexer are formed within a same integrated circuit.
Claim 8
Dependent Claim
291 words
A computer system comprising: a processor for initiating a burst read for a range of memory defined by a start address and a plurality of subsequent consecutive addresses; a burst logic circuit for generating consecutive addresses of a burst read sequence; a synchronous main emory bus coupled to the processor and the burst logic circuit, the synchronous main memory bus providing address signals and synchronous control signals including a clock signal and an address latch enable signal; a nonvolatile memory apparatus coupled to the burst logic circuit, comprising: a first bank of nonvolatile memory; a second bank of nonvolatile memory, wherein consecutive addresses of the nonvolatile memory apparatus are interlaced between the first and second banks; interlace control logic capable of receiving address signals, asynchronous control signals, and synchronous control signals including a clock signal; a mode register, wherein the interface control logic provides synchronous access to the first and second memor banks in accordance with the address signals and synchronous control signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing a first value, wherein the interface control logic provides asynchronous access to the first and second memor banks independent of the clock signal in accordance with the address signals and asynchronous control signals if the mode register is storing a second value; and a data multiplexer coupled to the first and second banks of nonvolatile memory, wherein the data multiplexer synchronously selects data from one of the first and second banks in accordance with the synchronous control signals and at least one bit of the address signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing the first value.
Claim 9
Dependent Claim
291 words
A computer system comprising: a processor for initiating a burst read for a range of memory defined by a start address and a plurality of subsequent consecutive addresses; a burst logic circuit for generating consecutive addresses of a burst read sequence; a synchronous main emory bus coupled to the processor and the burst logic circuit, the synchronous main memory bus providing address signals and synchronous control signals including a clock signal and an address latch enable signal; a nonvolatile memory apparatus coupled to the burst logic circuit, comprising: a first bank of nonvolatile memory; a second bank of nonvolatile memory, wherein consecutive addresses of the nonvolatile memory apparatus are interlaced between the first and second banks; interlace control logic capable of receiving address signals, asynchronous control signals, and synchronous control signals including a clock signal; a mode register, wherein the interface control logic provides synchronous access to the first and second memor banks in accordance with the address signals and synchronous control signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing a first value, wherein the interface control logic provides asynchronous access to the first and second memor banks independent of the clock signal in accordance with the address signals and asynchronous control signals if the mode register is storing a second value; and a data multiplexer coupled to the first and second banks of nonvolatile memory, wherein the data multiplexer synchronously selects data from one of the first and second banks in accordance with the synchronous control signals and at least one bit of the address signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing the first value.
Claim 10
Dependent Claim
14 words
The apparatus of claim 7 wherein the burst read sequence is a nonlinear sequence.
Claim 11
Dependent Claim
14 words
The apparatus of claim 7 wherein the burst read sequence is a linear sequence.
Claim 12
Dependent Claim
13 words
The apparatus of claim 7 wherein the nonvolatile memory is a flash memory.
Claim 13
Dependent Claim
16 words
The apparatus of claim 7 wherein the nonvolatile memory apparatus is formed in an integrated circuit.
Claim 14
Dependent Claim
22 words
The apparatus of claim 7 wherein the nonvolatile memory apparatus and the burst logic circuit are formed within a same integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |