DRAM variable row select

Claim 2

A bit select circuit for an integrated circuit comprising: a variable bit select circuit having inputs coupled to receive a plurality of address bits and a control signal, and having an output, at least one of the address bits being blocked or passed depending on said control signal; and an address decoder coupled to receive said output of said variable bit select circuit to enable access to memory data.

Claim 3

The circuit of claim 1 further comprising an address latch coupled to receive and latch said address bits, and to provide the address bits to said variable bit select circuit.

Claim 4

The circuit of claim 1 further comprising an output enable circuit coupled to receive the output of said variable bit select circuit and an address output enable signal, wherein said output enable circuit passes said output of said variable bit select circuit to said address decoder in response to the address output enable signal.

Claim 5

The circuit of claim 1 wherein when one of said address bits is blocked, said variable bit select circuit substitutes an active signal for the at least one blocked address bit.

Claim 6

The circuit of claim 1 wherein said variable bit select circuit includes at least one block/pass element coupled to receive the at least one address bit and the control signal, wherein the at least one block/pass element blocks or passes the at least one address bit in response to the control signal.

Claim 7

The circuit of claim 1 further comprising a variable bit select controller coupled to receive a controller enable signal and coupled to the variable bit select circuit, said variable bit select controller providing at least one block/pass control signal to said variable bit select circuit in response to the controller enable signal.

Claim 8

The circuit of claim 5 wherein the at least one block/pass element includes a selection transistor and a pull-up transistor each having a respective control electrode and a source-drain path, the control electrodes of the selection and pull-up transistors being coupled to said control signal, a source-drain path of the selection transistor being coupled to receive the at least one address bit and being coupled to an output line, said at least one address bit being selectively coupled to the output line in response to a first state of the control signal, the source-drain path of the pull-up transistor being coupled to a power supply and to the output line, and selectively coupling the power supply to the output line in response to a second state of the control signal.

Claim 9

A bit select circuit for a memory comprising: a plurality of address buffers coupled to receive a plurality of address bits including a variable bit select circuit coupled to receive at least one of the plurality of address bits and a control signal to provide an address buffer output, the at least one of the address bits being blocked or passed in response to said control signal; and an address decoder coupled to receive said address buffer output to enable access to memory data.

Claim 10

A bit select circuit for a memory comprising: a plurality of address buffers coupled to receive a plurality of address bits including a variable bit select circuit coupled to receive at least one of the plurality of address bits and a control signal to provide an address buffer output, the at least one of the address bits being blocked or passed in response to said control signal; and an address decoder coupled to receive said address buffer output to enable access to memory data.

Claim 11

The circuit of claim 8 wherein said variable bit select circuit includes at least one block/pass element coupled to receive the at least one address bit and the control signal, wherein the at least one block/pass element blocks or passes the at least one address bit in response to the control signal.

Claim 12

The circuit of claim 8 wherein said variable bit select circuit substitutes an active signal for the at least one blocked address bit.

Claim 13

The circuit of claim 8 wherein said bit select circuit constitutes a row address buffer circuit of a memory.

Claim 14

The circuit of claim 9 wherein the at least one block/pass element includes a selection transistor and a pull-up transistor each having a respective control electrode and a source-drain path, the control electrodes of the selection and pull-up transistors being coupled to said control signal, a source-drain path of the selection transistor being coupled to receive the at least one address bit and being coupled to an output line, said at least one address bit being selectively coupled to the output line in response to a first state of the control signal, the source-drain path of the pull-up transistor being coupled to a power supply and to the output line and selectively coupling the power supply to the output line in response to a second state of the control signal.

Claim 15

The circuit of claim 8 further comprising a variable bit select controller coupled to receive at least one controller enable signal, the variable bit select controller being coupled to the variable bit select circuit, said variable bit select controller providing said control signal to said variable bit select circuit in response to the at least one controller enable signal.

Claim 16

A bit select circuit for an integrated circuit comprising: a buffer circuit coupled to receive a plurality of address bits; a buffer latch circuit coupled to receive an output of said buffer circuit; a variable bit select circuit coupled to receive an output of said buffer latch circuit; a buffer output enable circuit coupled to receive an output of said variable bit select circuit; and an address decoder circuit coupled to receive an output of said buffer output enable circuit and to provide an output that enables access to memory data in response to the output of said variable bit select circuit.

Claim 17

A bit select circuit for an integrated circuit comprising: a buffer circuit coupled to receive a plurality of address bits; a buffer latch circuit coupled to receive an output of said buffer circuit; a variable bit select circuit coupled to receive an output of said buffer latch circuit; a buffer output enable circuit coupled to receive an output of said variable bit select circuit; and an address decoder circuit coupled to receive an output of said buffer output enable circuit and to provide an output that enables access to memory data in response to the output of said variable bit select circuit.

Claim 18

The circuit of claim 14 wherein said variable bit select circuit includes a variable bit select controller coupled to receive at least one signal that corresponds to a refresh mode of a memory device, and provides to said variable bit select circuit a control signal when the memory device is in the refresh mode.

Claim 19

A variable bit select circuit comprising: at least one selection transistor having a control electrode and a source-drain path, the control electrode of said selection transistor being coupled to a control signal, the source-drain path of the selection transistor being coupled to receive at least one address bit and being coupled to an output line, the at least one address bit being selectively coupled to the output line in response to a first state of the control signal; and at least one pull-up transistor having a control electrode and a source-drain path, the control electrode of the pull-up transistor being coupled to said control signal, the source-drain path of the pull-up transistor being coupled to receive a power supply signal and to the output line, and selectively coupling said power supply signal to the output line in response to a second state of the control signal.

Claim 20

A variable bit select circuit comprising: at least one selection transistor having a control electrode and a source-drain path, the control electrode of said selection transistor being coupled to a control signal, the source-drain path of the selection transistor being coupled to receive at least one address bit and being coupled to an output line, the at least one address bit being selectively coupled to the output line in response to a first state of the control signal; and at least one pull-up transistor having a control electrode and a source-drain path, the control electrode of the pull-up transistor being coupled to said control signal, the source-drain path of the pull-up transistor being coupled to receive a power supply signal and to the output line, and selectively coupling said power supply signal to the output line in response to a second state of the control signal.

Claim 21

The circuit of claim 16 further comprising: an address buffer coupled to receive the at least one address bit and coupled to said at least one selection transistor; and a decoder circuit coupled to the output line to provide a decoded output.

Claim 24

The method of claim 18 further comprising the steps of: buffering and latching said address bits prior to said passing or blocking steps; decoding said passed or substituted address bits into an address; and accessing memory cells that correspond to the decoded address.