Configuration data loopback in a bus bridge circuit

Claim 3

The method of claim 1, wherein the step of receiving an address over the first bus comprises the step of receiving the address over an address portion of the first bus.

Claim 4

The method of claim 2, wherein the step of transmitting the address received over the first bus over the second bus comprises the step of transmitting the address received over the first bus over the second bus during an address phase of the access cycle on the second bus.

Claim 5

The method of claim 3, wherein the step of decoding the address present on the second bus comprises the step of decoding the address present on the second bus during the address phase of the access cycle on the second bus.

Claim 6

The method of claim 4, wherein the step of bridging the data value to the access cycle on the second bus by transmitting the data value received over the first bus over the second bus comprises the step of transmitting the data value received over the first bus over the second bus during a data phase of the access cycle on the second bus.

Claim 7

The method of claim 5, wherein the step of receiving the data value present on the second bus comprises the step of receiving the data value present on the second bus during the data phase of the access cycle on the second bus.

Claim 8

A circuit for writing a configuration register in a bus bridge circuit, comprising: circuit for sensing an access cycle on a first bus, and receiving an address over the first bus; circuit for bridging the access cycle sensed on the first bus to an access cycle on a second bus by initiating the access cycle on the second bus and transmitting the address received over the first bus over the second bus without decoding the address received over the first bus: circuit for sensing the access cycle on the second bus, and decoding the address present on the second bus; circuit for receiving a data value over the first bus, the data value corresponding to the access cycle sensed on the first bus; circuit for bridging the data value to the access cycle on the second bus by transmitting the data value received over the first bus over the second bus; circuit for receiving the data value present on the second bus and storing the data value in the configuration register if the address decoded on the second bus selects the configuration register in the bus bridge circuit.

Claim 9

A circuit for writing a configuration register in a bus bridge circuit, comprising: circuit for sensing an access cycle on a first bus, and receiving an address over the first bus; circuit for bridging the access cycle sensed on the first bus to an access cycle on a second bus by initiating the access cycle on the second bus and transmitting the address received over the first bus over the second bus without decoding the address received over the first bus: circuit for sensing the access cycle on the second bus, and decoding the address present on the second bus; circuit for receiving a data value over the first bus, the data value corresponding to the access cycle sensed on the first bus; circuit for bridging the data value to the access cycle on the second bus by transmitting the data value received over the first bus over the second bus; circuit for receiving the data value present on the second bus and storing the data value in the configuration register if the address decoded on the second bus selects the configuration register in the bus bridge circuit.

Claim 10

The circuit of claim 7, wherein the circuit for receiving an address over the first bus comprises circuit for receiving the address over an address portion of the first bus.

Claim 11

The circuit of claim 8, wherein the circuit for transmitting the address received over the first bus over the second bus comprises circuit for transmitting the address received over the first bus over the second during an address phase of the access cycle on the second bus.

Claim 12

The circuit of claim 9, wherein the circuit for decoding the address present on the second bus comprises circuit for decoding the address present on the second bus during the address phase of the access cycle or the second bus.

Claim 13

The circuit of claim 10, wherein the circuit for bridging the data value to the access cycle on the second bus by transmitting the data value received over the first bus over the second bus comprises circuit for transmitting the data value received over the first bus over the second bus during a data phase of the access cycle on the second bus.

Claim 14

The circuit of claim 11, wherein the circuit for receiving the data value present on the second bus comprises circuit for receiving the data value present on the second bus during the data phase of the access cycle on the second bus.

Claim 15

A bus bridge circuit, comprising: control circuit containing at least one configuration register, the control circuit sensing an access cycle on a first bus, and receiving an address over the first bus, the control circuit bridging the access cycle sensed on the first bus to an access cycle on a second bus by initiating the access cycle on the second bus and transmitting the address received over the first bus over the second bus without decoding the address received over the first bus, the control circuit also sensing the access cycle on the second bus, and decoding the address present on the second bus, the control circuit receiving a data value present on the second bus and storing the data value in the configuration register if the address on the second bus selects the configuration register in the bus bridge circuit; data path circuit receiving the data value over the first bus, the data value corresponding to the access cycle sensed on the first bus, the data path circuit bridging the data value to the access cycle on the second bus by transmitting the data value received over the first bus over the second bus.

Claim 16

A bus bridge circuit, comprising: control circuit containing at least one configuration register, the control circuit sensing an access cycle on a first bus, and receiving an address over the first bus, the control circuit bridging the access cycle sensed on the first bus to an access cycle on a second bus by initiating the access cycle on the second bus and transmitting the address received over the first bus over the second bus without decoding the address received over the first bus, the control circuit also sensing the access cycle on the second bus, and decoding the address present on the second bus, the control circuit receiving a data value present on the second bus and storing the data value in the configuration register if the address on the second bus selects the configuration register in the bus bridge circuit; data path circuit receiving the data value over the first bus, the data value corresponding to the access cycle sensed on the first bus, the data path circuit bridging the data value to the access cycle on the second bus by transmitting the data value received over the first bus over the second bus.

Claim 17

The bus bridge circuit of claim 13, wherein the control circuit transmits the address received over the first bus over the second bus during an address phase of the access cycle on the second bus.

Claim 18

The bus bridge circuit of claim 14, wherein the control circuit decodes the address present on the second bus during the address phase of the access cycle on the second bus.

Claim 19

The bus bridge circuit of claim 15, wherein the data path circuit transmits the data value received over the first bus over the second bus during a data phase of the access cycle on the second bus.

Claim 20

The bus bridge circuit of claim 16, wherein the control circuit receives the data value present on the second bus during the data phase of the access cycle on the second bus.

Claim 21

A computer system, comprising: central processing means coupled for communication over a first bus; memory subsystem comprising dynamic random access memory; a plurality of peripheral components coupled for communication over a second bus; bus bridge circuit coupled to the memory subsystem and coupled for communication over the first bus and the second bus, the bus bridge circuit enabling access to the memory subsystem from the first bus and the second bus, the bridge circuit containing at least one configuration register for controlling the memory subsystem, the bus bridge circuit enabling a write access to the configuration register by translating an access cycle received over the first bus and targeted for the configuration register into an access cycle on the second bus targeted for the configuration register and writing the configuration register according to the access cycle on the second bus.

Claim 22

A computer system, comprising: central processing means coupled for communication over a first bus; memory subsystem comprising dynamic random access memory; a plurality of peripheral components coupled for communication over a second bus; bus bridge circuit coupled to the memory subsystem and coupled for communication over the first bus and the second bus, the bus bridge circuit enabling access to the memory subsystem from the first bus and the second bus, the bridge circuit containing at least one configuration register for controlling the memory subsystem, the bus bridge circuit enabling a write access to the configuration register by translating an access cycle received over the first bus and targeted for the configuration register into an access cycle on the second bus targeted for the configuration register and writing the configuration register according to the access cycle on the second bus.

Claim 23

The computer system of claim 50, wherein the bus bridge circuit comprises: circuit for sensing the access cycle on the first bus, and receiving an address over the first bus; circuit for bridging the access cycle sensed on the first bus to an access cycle on a second bus by initiating the access cycle on the second bus and transmitting the address received over the first bus over the second bus without decoding the address received over the first bus; circuit for sensing the access cycle on the second bus, and decoding the address present on the second bus; circuit for receiving a data value over the first bus, the data value corresponding to the access cycle sensed on the first bus; circuit for bridging the data value to the access cycle on the second bus by transmitting the data value received over the first bus over the second bus; circuit for receiving the data value present on the second bus and storing the data value in the configuration register if the address decoded on the second bus selects the configuration register.

Claim 24

The computer system of claim 19, wherein the circuit for receiving an address over the first bus comprises circuit for receiving the address over an address portion of the first bus.

Claim 25

The computer system of claim 20, wherein the circuit for transmitting the address received over the first bus over the second bus comprises circuit for transmitting the address received over the first bus over the second bus during an address phase of the access cycle on the second bus.

Claim 26

The computer system of claim 21, wherein the circuit for decoding the address present on the second bus comprises circuit for decoding the address present on the second bus during the address phase of the access cycle on the second bus.

Claim 27

The computer system of claim 22, wherein the circuit for bridging the data value to the access cycle on the second bus by transmitting the data value received over the first bus over the second bus comprises circuit for transmitting the data value received over the first bus over the second bus during a data phase of the access cycle on the second bus.

Claim 28

The computer system of claim 23, wherein the circuit for receiving the data value present on the second bus comprises circuit for receiving the data value present on the second bus during the data phase of the access cycle on the second bus.