Flash memory card with all zones chip enable circuitry

Claim 2

A flash memory card, comprising: (A) a plurality of flash memories, each having (1) an enable control input for selecting an active mode for the respective one of the plurality of flash memories upon receipt of a first signal and a standby mode for the respective one of the plurality of flash memories upon receipt of a second signal; (2) a power control input for selecting a power down mode for the respective one of the plurality of flash memories upon receipt of a third signal, wherein the power down mode overrides the active mode and the standby mode; (B) first addressable circuitry coupled to receive first data for causing all of the plurality of flash memories to operate in the active mode concurrently by generating the first signal and by causing the first signal to be concurrently applied to the enable control input of each of the plurality of flash memories upon receipt of the first data; (C) second addressable circuitry coupled to receive second data for causing all of the plurality of flash memories to be placed in the power down mode concurrently by generating the third signal and by causing the third signal to be concurrently applied to the power control input of each of the plurality of flash memories upon receipt of the second data regardless of the first data received by the first addressable circuitry.

Claim 3

The flash memory card of claim 1, further comprising (i) addressable power control circuitry for storing a first datum and a second datum, wherein the plurality of flash memories includes a first flash memory and a second flash memory; (ii) circuitry for (1) reading the first datum, and (2) applying the third signal to the power control input of the first flash memory if the first datum is in a first state, which places only the first flash memory in the power down mode, and (3) not applying the third signal to the power control input of the first flash memory if the first datum is in a second state, which permits the first flash memory to enter the active mode upon receipt of the first signal and the standby mode upon receipt of the second signal; (iii) circuitry for (1) reading the second datum, and (2) applying the third signal to the power control input of the second flash memory if the second datum is in the first state, which places only the second flash memory in the power down mode, and (3) not applying the third signal to the power control input of the second flash memory if the second datum is in the second state, which permits the second flash memory to enter the active mode upon receipt of the first signal and the standby mode upon receipt of the second signal; (iv) circuitry for altering the first and second data of the power control circuitry based upon a first address and third data supplied to the flash memory card.

Claim 4

The flash memory card of claim 2, further comprising circuitry for preserving the first and second data from a time before the first and second flash memories enter the power down mode until a time after the first and second flash memories leave the power down mode.