Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory

Claim 2

Circuitry within a FLASH EEPROM memory for indicating a state of the FLASH EEPROM memory to an external device, the FLASH EEPROM memory including a memory array and programming circuitry for programming and erasing the memory array, the circuitry comprising: (a) a state bus carrying a multiplicity of signals output by the programming circuitry; (b) a decoder coupled to the state bus and outputting a ready/busy signal, the ready/busy signal having a busy state and a ready state, the busy state indicating that the programming circuitry is programming or erasing the memory array, the ready state indicating that the programming circuitry is ready to begin programming or erasing the memory array; and (c) a driver circuit for receiving the ready/busy signal from the decoder and outputting a modified ready/busy signal to the external device, the modified ready/busy signal having a modified busy state and a modified ready state, the modified busy state being associated with the busy state and the modified ready state being associated with the ready state, the modified ready state interrupting the external device.

Claim 3

The circuitry of claim 1 wherein the driver circuit comprises: (a) a first inverter state having an input coupled to the ready/busy signal, the first inverter state having a first inverter output; (b) a second inverter stage having an input coupled to the ready/busy signal, the second inverter stage having a second inverter output; (c) a P channel field effect transistor having a gate coupled to the first inverter output, and a P channel output; and (d) an N channel field effect transistor having a gate coupled to the second inverter output and an N channel output coupled to the P-channel output and the sternal device.

Claim 4

The circuitry of claim 1 wherein the decoder comprises: (a) a first NAND gate having inputs coupled to a first set of signals carried by the state bus, the first NAND gate having a first NAND output; (b) a second NAND gate having inputs coupled to a second set of signals carried by the state bus, the second set of signals not including the first set of signals, the second NAND gate having a second NAND output; (c) a first NOR gate having inputs coupled to the first NAND output and the second NAND output, the first NOR gate having a NOR output; (d) a latch having an input coupled to the NOR output, the latch outputting the ready/busy signal.

Claim 5

The circuitry of claim 1 wherein the external device is a microprocessor.

Claim 6

Circuitry within a FLASH EEPROM memory for indicating a state of the FLASH EEPROM memory to an external device, the FLASH EEPROM memory including a memory array and programming circuitry for programming and erasing the memory array, the circuitry comprising: (a) a state bus coupled to the decoder, the state bus carrying the multiplicity of signals indicative of the current state of the programming circuitry; (b) a decoder coupled to the state bus for decoding a current state of the programming circuitry and outputting a multiplicity of decoded signals including a ready/busy signal, the ready/busy signal having a busy state and a ready state, the busy state indicating that the programming circuitry is busy programming or erasing the memory array, the ready state indicating that the programming circuitry is ready to begin programming or erasing the memory array; (c) a status register coupled to the decoder for storing the multiplicity of decoder signals; and (d) a driver circuit for receiving the ready/busy signal from the decoder and an outputting a modified ready/busy signal to the external device, the modified ready/busy signal having a modified busy state and a modified ready state, the modified busy state being associated with the busy state and the modified ready state being associated with the ready state, the modified ready state interrupting the external device.

Claim 7

Circuitry within a FLASH EEPROM memory for indicating a state of the FLASH EEPROM memory to an external device, the FLASH EEPROM memory including a memory array and programming circuitry for programming and erasing the memory array, the circuitry comprising: (a) a state bus coupled to the decoder, the state bus carrying the multiplicity of signals indicative of the current state of the programming circuitry; (b) a decoder coupled to the state bus for decoding a current state of the programming circuitry and outputting a multiplicity of decoded signals including a ready/busy signal, the ready/busy signal having a busy state and a ready state, the busy state indicating that the programming circuitry is busy programming or erasing the memory array, the ready state indicating that the programming circuitry is ready to begin programming or erasing the memory array; (c) a status register coupled to the decoder for storing the multiplicity of decoder signals; and (d) a driver circuit for receiving the ready/busy signal from the decoder and an outputting a modified ready/busy signal to the external device, the modified ready/busy signal having a modified busy state and a modified ready state, the modified busy state being associated with the busy state and the modified ready state being associated with the ready state, the modified ready state interrupting the external device.

Claim 8

The circuitry of claim 5 wherein the driver circuit comprises: (a) a first inverter stage having an input coupled to the ready/busy signal, the first inverter stage having a first inverter output; (b) a second inverter stage having an input coupled to the ready/busy signal, the second inverter stage having a second inverter output; (c) a P channel field effect transistor having a gate coupled to the first inverter output, and a P channel output; and (d) an N channel field effect transistor having a gate coupled to the second inverter output and an N channel output coupled to the P-channel output and the external device.

Claim 9

The circuitry of claim 5 wherein the decoder comprises: (a) a first NAND gate having inputs coupled to a first set of signals carried by the state bus, the first NAND gate having a first NAND output; (b) a second NAND gate having inputs coupled to a second set of signals carried by the sate bus, the second set of signals not including the first set of signals, the second NAND gate having a second NAND output; (c) a first NOR gate having inputs coupled to the first NAND output and the second NAND output, the first NOR gate having a NOR output; (d) a latch having an input coupled to the NOR output, the latch outputting the ready/busy signal.

Claim 10

The circuitry of claim 5 wherein the external device is a microprocessor.