Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin

Claim 2

An EEPROM formed in an integrated circuit and adapted to be either a read mode, a programming mode or an erase mode, said EEPROM comprising: means for receiving an address; decode means coupled to said means for receiving for determining whether said received address an address corresponding to an instruction to enter the programming mode, said code means also determining whether said received address is an address corresponding to an instruction to enter said erase mode; programming means coupled to said decode means for causing said EEPROM to go into said programming mode in respond to said decode means determining that said received address is an address corresponding to an instruction to enter said programming mode; erase means coupled to said decode means for causing said EEPROM to go into said erase mode in response to said decode means determining that said received address is an address corresponding to an instruction to enter said erase mode.

Claim 3

The EEPROM of claim 1 further comprising a lead coupled to aid programming means and erase means for receiving a programming voltage, said programming means and erase means being enabled in response to the voltage at said lead going from a first level to a second level, so that said programming means and erase means can cause said EEPROM to go into said programming mode or erase mode, and wherein said programming mean and erase means cause said EEPROM to go back into said read mode in response to the voltage at said lead going from said second level to said first level.

Claim 4

An EEPROM formed in an integrated circuit for being in either a read mode, a programming mode or an erase mode, said EEPROM comprising: a data bus including at least one data input lead for receiving data; data bus decode means for determining whether the data on said data bus is a value corresponding to an instruction to enter the programming mode, said data bus decode means also determining whether the data on said data bus is a value corresponding to an instruction to enter said erase mode; programming means coupled to aid data bus decode means for causing said EEPROM to go into said programming mode in response tot said data bus decode means determining that the data on said data bus is a value corresponding to an instruction to enter said programming mode; and erase means coupled to said data bus decode means for causing said EEPROM to go into said erase mode in response to said data bus decode means determining that the data on said data bus is a value corresponding to instruction to enter said erase mode.

Claim 5

An EEPROM formed in an integrated circuit for being in either a read mode, a programming mode or an erase mode, said EEPROM comprising: a data bus including at least one data input lead for receiving data; data bus decode means for determining whether the data on said data bus is a value corresponding to an instruction to enter the programming mode, said data bus decode means also determining whether the data on said data bus is a value corresponding to an instruction to enter said erase mode; programming means coupled to aid data bus decode means for causing said EEPROM to go into said programming mode in response tot said data bus decode means determining that the data on said data bus is a value corresponding to an instruction to enter said programming mode; and erase means coupled to said data bus decode means for causing said EEPROM to go into said erase mode in response to said data bus decode means determining that the data on said data bus is a value corresponding to instruction to enter said erase mode.

Claim 6

An erasable programmable memory adapted to being either a read mode, a programming mode, or an erase mode, said memory comprising: a data bus for receiving data; an address bus for receiving an address; address decode means coupled to said address bus for decoding said received address; and program and erase means coupled to said address decode means for causing said memory to go into said programming mode in response to the address on said address bus decoded by said address decode means when said address on said address bus is a value interpreted by said address decode means as an instruction to enter said programming mode, said program and erase means causing said memory to go into said erase mode in response to the address on said address bus decoded by said address decode means being a value interpreted by said address decode means as an instruction to enter said erase mode, and wherein if (a) said memory is in said programming mode, and (b) said memory receives an address on said address bus and data on said data bus, then (c) said memory stores said data in a location corresponding to said received address, even if said received address would have been interpreted as an instruction to enter said programming or erase mode had said memory not already been in said programming mode.

Claim 7

An erasable programmable memory adapted to being either a read mode, a programming mode, or an erase mode, said memory comprising: a data bus for receiving data; an address bus for receiving an address; address decode means coupled to said address bus for decoding said received address; and program and erase means coupled to said address decode means for causing said memory to go into said programming mode in response to the address on said address bus decoded by said address decode means when said address on said address bus is a value interpreted by said address decode means as an instruction to enter said programming mode, said program and erase means causing said memory to go into said erase mode in response to the address on said address bus decoded by said address decode means being a value interpreted by said address decode means as an instruction to enter said erase mode, and wherein if (a) said memory is in said programming mode, and (b) said memory receives an address on said address bus and data on said data bus, then (c) said memory stores said data in a location corresponding to said received address, even if said received address would have been interpreted as an instruction to enter said programming or erase mode had said memory not already been in said programming mode.

Claim 8

An erasable programmable memory for being in read mode, a programming mode, or an erase mode, said memory comprising: an address bus for receiving addresses; a data bus including at least one data input lead for receiving data; data bus decode means coupled to said data bus for decoding said received data; and program and erase means coupled to said data bus decode means for causing said memory to go into said programming mode in response to the data on said data bus decoded by said data bus decode means when said data bus decode means as an instruction to enter said programming mode, said program and erase means causing said memory to go into said erase mode in response to the data on said data bus being a value interpreted by said data bus decode means as an instruction to enter said erase mode, and wherein if (a) said memory is in said programming mode, and (b) said memory received an address on said address bus and data on said data bus, (c) aid memory stores dad received data in a location within said memory corresponding to said received address, even when said received data would have been interpreted as an instruction to enter either said programming or erase mode had said memory not already been in said programming mode.

Claim 9

An erasable programmable memory for being in read mode, a programming mode, or an erase mode, said memory comprising: an address bus for receiving addresses; a data bus including at least one data input lead for receiving data; data bus decode means coupled to said data bus for decoding said received data; and program and erase means coupled to said data bus decode means for causing said memory to go into said programming mode in response to the data on said data bus decoded by said data bus decode means when said data bus decode means as an instruction to enter said programming mode, said program and erase means causing said memory to go into said erase mode in response to the data on said data bus being a value interpreted by said data bus decode means as an instruction to enter said erase mode, and wherein if (a) said memory is in said programming mode, and (b) said memory received an address on said address bus and data on said data bus, (c) aid memory stores dad received data in a location within said memory corresponding to said received address, even when said received data would have been interpreted as an instruction to enter either said programming or erase mode had said memory not already been in said programming mode.

Claim 10

Memory of claim 5 further comprising: address decode means coupled to said address bus for decoding said received address, wherein said program and erase means is also coupled to said address decode means, and causes said memory to go into either said programming mode or erase mode in response to both the address on said address bus decoded by said address decode means and the data on said bus decoded by said data bus decode means.

Claim 11

A memory device comprising: first mean for receiving a first write signal; second means for receiving data; third means coupled to said first means for generating a second write signal, said third means causing said second write signal to go active in response to said first write signal going active a first time, said third means causing said second write signal to go inactive in response to said first write signal going active a second time after said first time; and memory means coupled to said second and third means for storing said received data in response to said second write signal.

Claim 12

A memory device comprising: first mean for receiving a first write signal; second means for receiving data; third means coupled to said first means for generating a second write signal, said third means causing said second write signal to go active in response to said first write signal going active a first time, said third means causing said second write signal to go inactive in response to said first write signal going active a second time after said first time; and memory means coupled to said second and third means for storing said received data in response to said second write signal.

Claim 13

The EEPROM of claim 1 wherein said programming means causes said EEPROM to go into said programming mode in response to said decode means determining that said received address is one of a plurality of addresses.

Claim 14

The EEPROM of claim 1 wherein said erase mean causes said EEPROM to go into said erase mode in response to said decode means determining that said received address is one of a plurality of predetermined addresses.

Claim 15

The EEPROM of claim 3 wherein said programming mean causes said EEPROM to go into said programming mode in response to said data bus decode means determining that said received data is one of a plurality of values.

Claim 16

The EEPROM of claim 3 wherein said erase means causes said EEPROM to go into said erase mode in response to said data bus decode means determining that said received data is one of a plurality of values.

Claim 17

A memory device comprising: address bus means for receiving addresses; data bus mean for receiving data; control means coupled to said address bus means for generating a signal, said signal going active when said address bus mean receives a first address, said signal going inactive when said address bus means receives a second address after receiving said first address; and memory means coupled to said control means and said data bus means for storing said received data in response to said signal.

Claim 18

A memory device comprising: address bus means for receiving addresses; data bus mean for receiving data; control means coupled to said address bus means for generating a signal, said signal going active when said address bus mean receives a first address, said signal going inactive when said address bus means receives a second address after receiving said first address; and memory means coupled to said control means and said data bus means for storing said received data in response to said signal.

Claim 19

The memory device of claim 12 wherein said first address equals said second address.

Claim 20

The memory device of claim 12 wherein said first and second addresses are provided by a microprocessor, said microprocessor performing tasks during the period between the times sad first and second addresses are provided.

Claim 23

The method of claim 15 further comprising the steps of: causing said EEPROM t go into said programming mode if said address is within a first plurality of predetermined values; and causing said EEPROM to go into an erase mode if said address is within a second plurality of predetermined values.

Claim 28

Method of claim 18 further comprising the steps of: causing said EEPROM to go into said programing mode if said data is within said first plurality of predetermined values, and causing said EEPROM to go into said erase mode if said data is within a second plurality of predetermined values.

Claim 29

EEPROM of claim 3 comprising: an address bus for receiving an address; and address decode means coupled to said address bus for decoding said received address, wherein said programming means and erase means is also coupled to said address decode means, and causes said EEPROM to go into either said programming mode or erase mode in response to both the address on said address bus decoded by said address decode means and the data on said data bus decoded by said data bus decode means.