Intelligent write in an EEPROM with data and erase check

Claim 2

A memory having a write mode for programming a selected memory location according to a data input signal, comprising: an array of memory locations, wherein a memory location is selected in response to an address, and each memory location is comprised of a set of memory cells, wherein each memory cell is in either a programmed or erased state; programming means, coupled to the array, for programming selected ones of the memory cells of a selected memory location from an erased state to a programmed state according to the data input signal; erasing means, coupled to the array, for erasing all of the memory cells of a selected location; reading means, coupled to the array, for reading the state of memory cells of a selected location and providing a data output signal representative of the state of the memory cells of the selected location; and control means for performing an initial program check by comparing the data input signal to the data output signal after the write mode has been entered but prior to erasing the selected location, for providing a ready signal is the data input signal is the same as the data output signal, for causing the erase means to erase the selected memory location is the data input signal is not the same as the data output signal, and for performing an erase check by determining if all of the memory cells in the selected location are in the erased state after performing the initial program check but before performing an erase of the memory cells of the selected location.

Claim 3

The memory of claim 1 wherein the control means is further characterized as causing the programming means to program the selected memory location if the memory cells of the selected location are all erased, and as causing the erase means to erase the selected memory location if all of the memory cells of the selected location are not erased.

Claim 4

In a memory comprised of an array of memory locations in which each memory location has data present therein and is comprised of a plurality of memory cells which can be selectively programmed if all of the memory cells of the memory location are in an erased state, a write mode for programming a selected memory location with data to be written comprising the steps of: determining if the data present in the memory location is the same as the data to be written; terminating the write mode if the data to be written is the same as the data present in the selected memory location; determining if the memory location is erased before erasing the memory location; erasing the memory location if the memory location is not erased; and programming the memory location if the memory location is erased.

Claim 5

In a memory comprised of an array of memory locations in which each memory location has data present therein and is comprised of a plurality of memory cells which can be selectively programmed if all of the memory cells of the memory location are in an erased state, a write mode for programming a selected memory location with data to be written comprising the steps of: determining if the data present in the memory location is the same as the data to be written; terminating the write mode if the data to be written is the same as the data present in the selected memory location; determining if the memory location is erased before erasing the memory location; erasing the memory location if the memory location is not erased; and programming the memory location if the memory location is erased.

Claim 6

A memory having a write mode for programming a selected memory location according to a data input signal, comprising: a memory array having intersecting erase lines and word lines with a memory location at each intersection wherein each memory location comprises a plurality of memory cells coupled to a word line and an erase line, and having a plurality of bit lines in which each memory cell is coupled to a corresponding bit line; a row decoder for enabling a selected word line in response to a row address; a column decoder for selecting an erase line and a corresponding plurality of bit lines in response to a column address; a sense amplifier, coupled to the column decoder, for sensing data from selected bit lines coupled thereto by the column decoder and providing a data out signal representative of the data sensed; a data in driver, coupled to the column decoder, for providing a write input signal, in response to the data input signal, to selected bit lines coupled thereto by the column decoder for programming a memory location corresponding to the selected bit lines and enabled word line; and control means for performing an initial program check by comparing the data input signal to the data output signal after the write mode has been entered but prior to erasing the selected location, for providing a ready signal if the data input signal is the same as the data output signal, for enabling the erase line to erase the selected memory location if the data input signal is not the same as the data output signal, and for performing an erase check by determining if all of the memory cells in the selected location are in the erased state after performing the initial program check but before performing an erase of the memory cells of the selected location.

Claim 7

A memory having a write mode for programming a selected memory location according to a data input signal, comprising: a memory array having intersecting erase lines and word lines with a memory location at each intersection wherein each memory location comprises a plurality of memory cells coupled to a word line and an erase line, and having a plurality of bit lines in which each memory cell is coupled to a corresponding bit line; a row decoder for enabling a selected word line in response to a row address; a column decoder for selecting an erase line and a corresponding plurality of bit lines in response to a column address; a sense amplifier, coupled to the column decoder, for sensing data from selected bit lines coupled thereto by the column decoder and providing a data out signal representative of the data sensed; a data in driver, coupled to the column decoder, for providing a write input signal, in response to the data input signal, to selected bit lines coupled thereto by the column decoder for programming a memory location corresponding to the selected bit lines and enabled word line; and control means for performing an initial program check by comparing the data input signal to the data output signal after the write mode has been entered but prior to erasing the selected location, for providing a ready signal if the data input signal is the same as the data output signal, for enabling the erase line to erase the selected memory location if the data input signal is not the same as the data output signal, and for performing an erase check by determining if all of the memory cells in the selected location are in the erased state after performing the initial program check but before performing an erase of the memory cells of the selected location.

Claim 8

The memory of claim 4 wherein the control means is further characterized as causing the data in driver to program the selected memory location is the memory cells of the selected memory location are all erased, and as enabling the erase line to erase the selected memory location if all of the memory cells of the selected memory location are not erased.