System for simultaneously programming a number of EPROMs

Claim 1

A system for simultaneously programming a plurality of erasable programmable read only memory devices (EPROMs), each having a number of memory sites that are each initially set in all-ones condition, which comprises: a central processing unit; means for rotating a program comprising a plurality of successive bytes from a master memory device and storing said program in said central processing unit; a cabinet rack for receiving multiple circuit boards each having several EPROMs, each having all of its memory sites set in the "all-ones" condition; an interface circuit interposed between said cabinet rack and said central processing unit for transmitting successive bytes comprising bits of ones and zeros to set each memory site accordingly and for subsequently reading the setting of each memory site back into said central processing unit; means within the central processing unit for transferring each byte of the program to said interface circuit for impression at successive memory sites; means within the central processing unit for recognizing bytes of all ones and blocking the impression of said "all-ones" bytes-bits to said interface; and means within the central processing unit for receiving through said interface circuit the byte setting of each programmed memory site and for verifying said setting with respect to the byte impressed through the interface circuit to the memory site, and for verifying the "all-ones" setting of those memory sites associated with the blocked "all-ones" byte recognized in the central processing unit.

Claim 2

A system for simultaneously programming a plurality of erasable programmable read only memory devices (EPROMs), each having a number of memory sites that are each initially set in all-ones condition, which comprises: a central processing unit; means for rotating a program comprising a plurality of successive bytes from a master memory device and storing said program in said central processing unit; a cabinet rack for receiving multiple circuit boards each having several EPROMs, each having all of its memory sites set in the "all-ones" condition; an interface circuit interposed between said cabinet rack and said central processing unit for transmitting successive bytes comprising bits of ones and zeros to set each memory site accordingly and for subsequently reading the setting of each memory site back into said central processing unit; means within the central processing unit for transferring each byte of the program to said interface circuit for impression at successive memory sites; means within the central processing unit for recognizing bytes of all ones and blocking the impression of said "all-ones" bytes-bits to said interface; and means within the central processing unit for receiving through said interface circuit the byte setting of each programmed memory site and for verifying said setting with respect to the byte impressed through the interface circuit to the memory site, and for verifying the "all-ones" setting of those memory sites associated with the blocked "all-ones" byte recognized in the central processing unit.