Memory device

Claim 2

A memory device comprising a plurality of word lines, a plurality of digit line pairs, each of said digit line pairs including first and second digit lines, a plurality of static type memory cells arranged at the intersections of said word lines and said digit line pairs, means for receiving address signals, a word decoder having a plurality of output terminals each coupled to corresponding one of said word lines, means for receiving a control signal, first means coupled to said word decoder for forcibly set all the output terminals of said word decoder at a selection level irrespectively of said address signals in response to said control signal, and second means for forcibly setting all the first digit lines of said digit line pairs at the same predetermined logic state in response to said control signal.

Claim 3

The memory device according to claim 1, in which said word decoder includes a plurality of NOR gates and said first means includes a plurality of transistors coupled between all the input terminals of said word decoder and a reference potential point and having control electrodes to which said control signal is applied.

Claim 4

The circuit according to claim 1, in which said second means includes a plurality of first transistors each coupled between the corresponding one of said first digit lines and a reference potential point and a plurality of second transistors each coupled between the corresponding one of said second digit lines and a power supply potential point, and means control electrodes of said first and second transistors with said control signal.

Claim 5

The memory device according to claim 1 further comprising a plurality of address inverter buffers coupled to said word decoder, each of said address inverter buffers receiving one of said address signals to generate its true and complementary signals.

Claim 6

The memory device according to claim 1, further comprising a plurality of transistors coupled between said first digit lines and a power supply potential point and means for making said transistors non-conducting in response to presence of said control signal and making them conducting in response to absence to said control signal.

Claim 7

A memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells arranged at the intersections of said word lines and said digit lines, a plurality of address terminals for receiving address signals, a plurality of address inverter buffers each coupled to each of said address terminals for generating true and complementary signals at its output terminals with respect to the address signal at said address terminals, a word decoder having a plurality of output terminals each coupled to each of said word lines and a plurality of input terminals coupled to the output terminals of said address inverter buffers, a control terminal for receiving a control signal, a plurality of clamp means coupled with said control terminal, each of said clamp means being coupled between each of said output terminals of said address inverter buffers and a reference potential point and operatively clamping potentials at said output terminals of said address inverter buffers at said reference potential in response to said control signal, and a plurality of set means each coupled to said control terminal and to each of said digit lines for operatively setting said digit lines at a predetermined logic state in response to said control signal.

Claim 8

A memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells arranged at the intersections of said word lines and said digit lines, a plurality of address terminals for receiving address signals, a plurality of address inverter buffers each coupled to each of said address terminals for generating true and complementary signals at its output terminals with respect to the address signal at said address terminals, a word decoder having a plurality of output terminals each coupled to each of said word lines and a plurality of input terminals coupled to the output terminals of said address inverter buffers, a control terminal for receiving a control signal, a plurality of clamp means coupled with said control terminal, each of said clamp means being coupled between each of said output terminals of said address inverter buffers and a reference potential point and operatively clamping potentials at said output terminals of said address inverter buffers at said reference potential in response to said control signal, and a plurality of set means each coupled to said control terminal and to each of said digit lines for operatively setting said digit lines at a predetermined logic state in response to said control signal.

Claim 9

The memory device according to claim 6, in which each of said clamp means includes a transistor coupled between said one of said output terminals of said address inverter buffers and said reference potential point and having a control electrode coupled to said control terminal.

Claim 10

The memory device according to claim 6, in which each of said set means includes a transistor coupled between said one of said digit lines and a predetermined potential point and having a control electrode coupled to said control terminal.

Claim 11

A memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells arranged at the intersections of said word lines and said digit lines, means for receiving address input signals, a control terminal for receiving a control signal having first and second logic levels, a word decoder having a plurality of output terminals coupled to said word lines, first means coupled to said word decoder for forcibly setting said output terminals of said word decoder at a selection levels in response to said first logic levels, a plurality of switch means each coupled one of said digit lines and a reference potential point, and means coupled to said control terminal for enabling said plurality of switch means in response to said second logic level of said control signal and disenabling them in response to said first logic level of said control signal.

Claim 12

A memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells arranged at the intersections of said word lines and said digit lines, means for receiving address input signals, a control terminal for receiving a control signal having first and second logic levels, a word decoder having a plurality of output terminals coupled to said word lines, first means coupled to said word decoder for forcibly setting said output terminals of said word decoder at a selection levels in response to said first logic levels, a plurality of switch means each coupled one of said digit lines and a reference potential point, and means coupled to said control terminal for enabling said plurality of switch means in response to said second logic level of said control signal and disenabling them in response to said first logic level of said control signal.

Claim 13

The memory device according to claim 9, in which each of said memory cells is of a static type.