Burst access memory

Claim 1

An apparatus comprising: first and second address counters; addressing means for loading address values into said first and second address counters; first and second memory arrays; address multiplexing means for selectively applying the address values loaded in said first and second address counters to said first and second memory arrays and to supply address values to said first and second memory arrays simultaneously; first and second reversible FIFOs; first and second data ports, connected to said first and second reversible FIFOs respectively, data multiplexing means for selectively connecting said first and second reversible FIFOs simultaneously to said first and second memory arrays; control means for controlling the operation of said first and second reversible FIFOs and said data multiplexing means to supply data words from said first and second reversible FIFOs to said first and second memory arrays in a write access mode of operation, and to selectively supply data words stored in said first and second memory arrays to said first and second FIFOs in a read access mode of operation, and to simultaneously supply data words to and from said memory arrays during write access mode and read access modes, respectively, and to synchronize addressing said first and second memory arrays utilizing said FIFOs; and wherein said first and second data ports transfer data words simultaneously when said first and second data ports are in a burst mode.

Claim 2

An apparatus comprising: first and second address counters; addressing means for loading address values into said first and second address counters; first and second memory arrays; address multiplexing means for selectively applying the address values loaded in said first and second address counters to said first and second memory arrays and to supply address values to said first and second memory arrays simultaneously; first and second reversible FIFOs; first and second data ports, connected to said first and second reversible FIFOs respectively, data multiplexing means for selectively connecting said first and second reversible FIFOs simultaneously to said first and second memory arrays; control means for controlling the operation of said first and second reversible FIFOs and said data multiplexing means to supply data words from said first and second reversible FIFOs to said first and second memory arrays in a write access mode of operation, and to selectively supply data words stored in said first and second memory arrays to said first and second FIFOs in a read access mode of operation, and to simultaneously supply data words to and from said memory arrays during write access mode and read access modes, respectively, and to synchronize addressing said first and second memory arrays utilizing said FIFOs; and wherein said first and second data ports transfer data words simultaneously when said first and second data ports are in a burst mode.

Claim 7

An apparatus comprising: first and second address counters which are incremented in accordance with a clock cycle during a burst mode of operation; addressing means for loading address values into said first and second address counters; first and second memory arrays wherein said first array contains even addresses and said second array contains odd addresses; first and second data ports, corresponding to said first and second address counters, said data ports capable of being simultaneously active in said burst mode of operation, and said data ports each transferring one data word per clock cycle while simultaneously active in said burst mode; address multiplexing means for applying, during burst mode access, even address values from said first and second address counters to said first memory array and to supply odd address values from said first and second address counters to said second memory array, said multiplexing means supplying even and odd addresses to said first and second arrays simultaneously, synchronization means connected between said memory arrays and said data ports, for maintaining even and odd address synchronization between said data ports when burst mode access is stopped and then restarted on one of said data ports, thereby minimizing delay on restart.

Claim 8

An apparatus comprising: first and second address counters which are incremented in accordance with a clock cycle during a burst mode of operation; addressing means for loading address values into said first and second address counters; first and second memory arrays wherein said first array contains even addresses and said second array contains odd addresses; first and second data ports, corresponding to said first and second address counters, said data ports capable of being simultaneously active in said burst mode of operation, and said data ports each transferring one data word per clock cycle while simultaneously active in said burst mode; address multiplexing means for applying, during burst mode access, even address values from said first and second address counters to said first memory array and to supply odd address values from said first and second address counters to said second memory array, said multiplexing means supplying even and odd addresses to said first and second arrays simultaneously, synchronization means connected between said memory arrays and said data ports, for maintaining even and odd address synchronization between said data ports when burst mode access is stopped and then restarted on one of said data ports, thereby minimizing delay on restart.

Claim 20

An apparatus comprising: first and second address counters which are incremented in accordance with a clock cycle during a burst mode of operation; addressing means for loading address values into said first and second address counters; first and second memory arrays wherein said first array contains even addresses and said second array contains odd addresses; first and second data ports, corresponding to said first and second address counters, said data ports capable of being simultaneously active in said burst mode of operation, and said data ports each transferring one data word per clock cycle while simultaneously active in said burst mode; address multiplexing means for applying, during burst mode access, even address values from said first and second address counters to said first memory array and to supply odd address values from said first and second address counters to said second memory array, said multiplexing means supplying even and odd addresses to said first and second arrays simultaneously; synchronization means connected between said memory arrays and said data ports, for maintaining even and odd address synchronization between said data ports when burst mode access is stopped and then restarted on one of said data ports, thereby minimizing delay on restart; said synchronization means comprising first and second reversible FIFOs, corresponding to said first and second data ports respectively; a phase means for controlling an odd and even phase of said apparatus, and providing a phase signal indicating said phase; and wherein one of said ports transfers data in a burst mode while the other port is in a random access mode.

Claim 21

An apparatus comprising: first and second address counters which are incremented in accordance with a clock cycle during a burst mode of operation; addressing means for loading address values into said first and second address counters; first and second memory arrays wherein said first array contains even addresses and said second array contains odd addresses; first and second data ports, corresponding to said first and second address counters, said data ports capable of being simultaneously active in said burst mode of operation, and said data ports each transferring one data word per clock cycle while simultaneously active in said burst mode; address multiplexing means for applying, during burst mode access, even address values from said first and second address counters to said first memory array and to supply odd address values from said first and second address counters to said second memory array, said multiplexing means supplying even and odd addresses to said first and second arrays simultaneously; synchronization means connected between said memory arrays and said data ports, for maintaining even and odd address synchronization between said data ports when burst mode access is stopped and then restarted on one of said data ports, thereby minimizing delay on restart; said synchronization means comprising first and second reversible FIFOs, corresponding to said first and second data ports respectively; a phase means for controlling an odd and even phase of said apparatus, and providing a phase signal indicating said phase; and wherein one of said ports transfers data in a burst mode while the other port is in a random access mode.