US4947373A
Expired / Lapsed
US
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Dynamic ram
Assignee: Hitachi Ltd
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Filing: 1987-12-17
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Granted: 1990-08-07
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Expires: 2007-12-17
Abstract
Abstract A semiconductor memory is provided with a first memory cell group, a second memory cell group, a first register for a serial output operation for holding information related to the first memory cell group, a second register for a serial output operation for holding information related to the second memory cell group, and transfer means for transferring information related to either the first or second memory cell group to either the first or second serial output register. By virtue of this arrangement, while the information transferred to the first serial output register is being serially output therefrom, information can simultaneously be transferred to the second serial output register by the transfer means.
Inventors
- 👤 Yasunori Yamaguchi
- 👤 Katsuyuki Sato
- 👤 Jun Mitake
- 👤 Hitoshi Kawaguchi
- 👤 Masahiro Yoshida
- 👤 Terutaka Okada
- 👤 Makoto Morino
- 👤 Tetsuya Saeki
- 👤 Yosuke Yukawa
- 👤 Osamu Nagashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
256 words
A dual port semiconductor memory comprising: a memory cell array including a plurality of word lines, a plurality of data lines and a plurality of memory cells coupled to intersections of said word lines and data lines such that said memory cells have control terminals thereof coupled to the word lines and data input/output terminals thereof coupled to the data lines; a random access input/output circuit coupled to said memory cell array to provide random access to said memory cell array in accordance with addresses supplied from an external terminal coupled to said random access input/output circuit; a first serial access data register coupled to said data lines of said memory cell array; a second serial access data register coupled to said data lines of said memory cell array; means coupled to said first and second serial access data registers to permit transfer of data between said data lines and either one of said first and second serial access data registers; a serial input/output circuit; means for coupling said first and second serial access registers to said serial input/output circuit; and means for controlling the connection of the first and second serial access data registers to said data lines and to said serial input/output circuit so that said data previously transferred to one of said first and second serial access data registers is transferred to said serial input/output circuit registers is coupled to said data lines to allow information transfer between said data lines and said other of said first and second serial access data registers.
Claim 2
Dependent Claim
256 words
A dual port semiconductor memory comprising: a memory cell array including a plurality of word lines, a plurality of data lines and a plurality of memory cells coupled to intersections of said word lines and data lines such that said memory cells have control terminals thereof coupled to the word lines and data input/output terminals thereof coupled to the data lines; a random access input/output circuit coupled to said memory cell array to provide random access to said memory cell array in accordance with addresses supplied from an external terminal coupled to said random access input/output circuit; a first serial access data register coupled to said data lines of said memory cell array; a second serial access data register coupled to said data lines of said memory cell array; means coupled to said first and second serial access data registers to permit transfer of data between said data lines and either one of said first and second serial access data registers; a serial input/output circuit; means for coupling said first and second serial access registers to said serial input/output circuit; and means for controlling the connection of the first and second serial access data registers to said data lines and to said serial input/output circuit so that said data previously transferred to one of said first and second serial access data registers is transferred to said serial input/output circuit registers is coupled to said data lines to allow information transfer between said data lines and said other of said first and second serial access data registers.
Claim 3
Dependent Claim
111 words
A dual port semiconductor memory circuit according to claim 7, wherein said means for controlling the connection of the first and second serial access data registers comprises a first plurality of switching means coupled between the data lines of the memory array and the first and second serial access data registers, a second plurality of switching means coupled between the first and second serial access data registers and the serial input/output circuit and control means for controlling the operation of the first and second pluralities of switching means to control the connection of the first and second serial access data registers to the data lines and to the serial input/output circuit.
Claim 4
Dependent Claim
249 words
A semiconductor memory comprising: a memory cell array including a first word line, a second word line, a first plurality of memory cells having respective select terminals thereof mutually coupled to said first word line, a plurality of data lines to which are respectively coupled to input/output terminals of said plurality of memory cells, and a second plurality of memory cells having respective select terminals thereof mutually coupled to said second word line and having input/output terminals thereof respectively coupled to said plurality of data lines; first storage means for storing readout information from said plurality of memory cells coupled to said first word line; second storage means for storing readout information from said plurality of memory cells coupled to said second word line; means coupled to said first and second storage means to permit transfer of data between said data lines and either one of said first and second storage means; a serial output circuit; means for coupling said first and second storage means to said serial output circuit; and means for controlling the connection of the first and second storage means to said data lines and to said serial output circuit so that said data previously transferred to one of said first and second storage means is transferred to said serial output circuit while the other of said first and second storage means is coupled to said data lines to allow information transfer between said data lines and said other of said first and second storage means.
Claim 5
Dependent Claim
249 words
A semiconductor memory comprising: a memory cell array including a first word line, a second word line, a first plurality of memory cells having respective select terminals thereof mutually coupled to said first word line, a plurality of data lines to which are respectively coupled to input/output terminals of said plurality of memory cells, and a second plurality of memory cells having respective select terminals thereof mutually coupled to said second word line and having input/output terminals thereof respectively coupled to said plurality of data lines; first storage means for storing readout information from said plurality of memory cells coupled to said first word line; second storage means for storing readout information from said plurality of memory cells coupled to said second word line; means coupled to said first and second storage means to permit transfer of data between said data lines and either one of said first and second storage means; a serial output circuit; means for coupling said first and second storage means to said serial output circuit; and means for controlling the connection of the first and second storage means to said data lines and to said serial output circuit so that said data previously transferred to one of said first and second storage means is transferred to said serial output circuit while the other of said first and second storage means is coupled to said data lines to allow information transfer between said data lines and said other of said first and second storage means.
Claim 6
Dependent Claim
101 words
A semiconductor memory according to claim 3, wherein said means for controlling the connection of the first and second storage means comprises a first plurality of switching means coupled between the data lines of the memory cell array and the first and second storage means, a second plurality of switching means coupled between the first and second storage means and the serial output circuit, and control means for controlling the operation of the first and second pluralities of switching means to control the connection of the first and second storage means to the data lines and to the serial output circuit.
Claim 7
Dependent Claim
24 words
A semiconductor memory according to claim 4, wherein said each memory cell includes a series connection comprising a switching MISFET and a storage capacitor.
Claim 8
Dependent Claim
140 words
A semiconductor memory comprising: a sense amplifier; a pair of memory arrays disposed at both sides, respectively, of said sense amplifier and connected to said sense amplifier so that said sense amplifier is shared by said memory arrays; a serial input/output circuit coupled to be used in common by said pair of memory arrays; storage means coupled between said pair of memory arrays and said serial input/output circuit, said storage means including means for storing readout information from either one of said pair of memory arrays, wherein said storage means and said serial input/output circuit operate to provide a serial output of readout information stored in said storage means; and means coupled to said sense amplifier and said memory arrays to operatively couple only one memory array of said pair of memory arrays to said sense amplifier at a time.
Claim 9
Dependent Claim
140 words
A semiconductor memory comprising: a sense amplifier; a pair of memory arrays disposed at both sides, respectively, of said sense amplifier and connected to said sense amplifier so that said sense amplifier is shared by said memory arrays; a serial input/output circuit coupled to be used in common by said pair of memory arrays; storage means coupled between said pair of memory arrays and said serial input/output circuit, said storage means including means for storing readout information from either one of said pair of memory arrays, wherein said storage means and said serial input/output circuit operate to provide a serial output of readout information stored in said storage means; and means coupled to said sense amplifier and said memory arrays to operatively couple only one memory array of said pair of memory arrays to said sense amplifier at a time.
Claim 10
Dependent Claim
41 words
A semiconductor memory according to claim 6, wherein said means comprises a first switching means coupled between one of said memory arrays and the sense amplifier and a second switching means coupled between the other memory array and the sense amplifier.
Claim 11
Dependent Claim
291 words
A semiconductor memory comprising: a pair of memory arrays each including a first word line, a second word line, a first plurality of memory cells having respective select terminals thereof mutually coupled to said first word line, a plurality of data lines to which are respectively coupled to input/output terminals of said plurality of memory cells, and a second plurality of memory cells having respective select terminals thereof mutually coupled to said second word line and having input/output terminals thereof respectively coupled to said plurality of data lines; first storage means for storing readout information from said plurality of memory cells coupled to said first word line; second storage means for storing readout information from said plurality of memory cells coupled to said second word line; means coupled to said first and second storage means to permit transfer of data between said data lines and either one of said first and second storage means; a serial output circuit; means for coupling said first and second storage means to said serial output circuit; means for controlling the connection of the first and second storage means to said data lines and to said serial output circuit so that said data previously transferred to one of said first and second storage means is transferred to said serial output circuit while the other of said first and second storage means is coupled to said data lines to allow information transfer between said data lines and said other of said first and second storage means; a sense amplifier coupled between said pair of memory arrays; and means coupled to said sense amplifier and said memory arrays to operatively couple only one memory array of said pair of memory arrays to said sense amplifier at a time.
Claim 12
Dependent Claim
291 words
A semiconductor memory comprising: a pair of memory arrays each including a first word line, a second word line, a first plurality of memory cells having respective select terminals thereof mutually coupled to said first word line, a plurality of data lines to which are respectively coupled to input/output terminals of said plurality of memory cells, and a second plurality of memory cells having respective select terminals thereof mutually coupled to said second word line and having input/output terminals thereof respectively coupled to said plurality of data lines; first storage means for storing readout information from said plurality of memory cells coupled to said first word line; second storage means for storing readout information from said plurality of memory cells coupled to said second word line; means coupled to said first and second storage means to permit transfer of data between said data lines and either one of said first and second storage means; a serial output circuit; means for coupling said first and second storage means to said serial output circuit; means for controlling the connection of the first and second storage means to said data lines and to said serial output circuit so that said data previously transferred to one of said first and second storage means is transferred to said serial output circuit while the other of said first and second storage means is coupled to said data lines to allow information transfer between said data lines and said other of said first and second storage means; a sense amplifier coupled between said pair of memory arrays; and means coupled to said sense amplifier and said memory arrays to operatively couple only one memory array of said pair of memory arrays to said sense amplifier at a time.
Claim 13
Dependent Claim
311 words
A dual port semiconductor memory comprising: a pair of memory cell arrays each including a plurality of word lines, a plurality of data lines and a plurality of memory cells coupled to intersections of said word lines and data lines such that said memory cells have control terminals thereof coupled to the word lines and data input/output terminals thereof coupled to the data lines; a random access input/output circuit coupled to said memory cell array to provide random access to said memory cell array in accordance with addresses supplied from an external terminal coupled to said random access input/output circuit; a first serial access data register coupled to said data lines of said memory cell array; a second serial access data register coupled to said data lines of said memory cell array; means coupled to said first and second serial access data registers to permit transfer of data between said data lines and either one of said first and second serial access data registers; a serial input/output circuit; means for coupling said first and second serial access registers to said serial input/output circuit; means for controlling the connection of the first and second serial access data registers to said data lines and to said serial input/output circuit so that said data previously transferred to one of said first and second serial access data registers is transferred to said serial input/output circuit while the other of said first and second serial access data registers is coupled to said data lines to allow information transfer between said data lines and said other of said first and second serial access data registers; a sense amplifier coupled between said pair of memory cell arrays; and means coupled to said sense amplifier and said memory arrays to operatively couple only one memory array of said pair of memory arrays to said sense amplifier at a time.
Claim 14
Dependent Claim
311 words
A dual port semiconductor memory comprising: a pair of memory cell arrays each including a plurality of word lines, a plurality of data lines and a plurality of memory cells coupled to intersections of said word lines and data lines such that said memory cells have control terminals thereof coupled to the word lines and data input/output terminals thereof coupled to the data lines; a random access input/output circuit coupled to said memory cell array to provide random access to said memory cell array in accordance with addresses supplied from an external terminal coupled to said random access input/output circuit; a first serial access data register coupled to said data lines of said memory cell array; a second serial access data register coupled to said data lines of said memory cell array; means coupled to said first and second serial access data registers to permit transfer of data between said data lines and either one of said first and second serial access data registers; a serial input/output circuit; means for coupling said first and second serial access registers to said serial input/output circuit; means for controlling the connection of the first and second serial access data registers to said data lines and to said serial input/output circuit so that said data previously transferred to one of said first and second serial access data registers is transferred to said serial input/output circuit while the other of said first and second serial access data registers is coupled to said data lines to allow information transfer between said data lines and said other of said first and second serial access data registers; a sense amplifier coupled between said pair of memory cell arrays; and means coupled to said sense amplifier and said memory arrays to operatively couple only one memory array of said pair of memory arrays to said sense amplifier at a time.
Claim 15
Dependent Claim
70 words
A semiconductor memory according to claim 3, wherein each of said first and second storage means is comprised of a plurality of unit data registers respectively coupled to predetermined data line pairs of said plurality of data lines, and wherein said control means includes means for selecting a predetermined one of said unit data registers for transferring data between said selected unit data register and a predetermined data line pair.
Claim 16
Dependent Claim
72 words
A semiconductor memory according to claim 1, wherein each of said first and second serial access data registers is comprised of a plurality of unit data registers respectively coupled to predetermined data line pairs of said plurality of data lines, and wherein said control means includes means for selecting a predetermined one of said unit data registers for transferring data between said selected unit data register and a predetermined data line pair.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-06 | 1994-02-05 | 1994-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-06 | 1998-02-05 | 1998-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-06 | 2002-02-05 | 2002-08-07 | $7700.00 | Window Closed / Lapsed |