US5202856A
Expired / Lapsed
US
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Method and apparatus for simultaneous, interleaved access of multiple memories by multiple ports
Assignee: EMC Corp
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Filing: 1990-04-05
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Granted: 1993-04-13
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Expires: 2010-04-05
Abstract
Abstract A memory system having multiple memories and multiple ports. Multiplexing logic couples each of the ports to each of the memories. A sequencing circuit controls the multiplexers so that each port is sequentially coupled to each of the memories in sequence in a repeating cycle. When coupled to each memory, a block of data is transferred. A second port is coupled to a different memory at each point in time, with the two ports being switched simultaneously to avoid overlap. A port desiring access to the system must wait until it can fit into this switching queue so that it can transfer in lock-step with the other ports to a different memory. Each port has a data I/O bus, an address input bus, an address counter and R/W controls.
Inventors
- 👤 Joseph S. Glider
- 👤 Kaushik S. Shah
- 👤 Edward E. Asato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:46
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1647; G11; G11C; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
102 words
A memory buffering system comprising: a plurality of memories; a plurality of data ports; multiplexing means for selectively coupling each of said data ports to each of said memories; and sequencing means, coupled to said multiplexing means, for providing control signals to said multiplexing means to alternately couple said data ports to each of said memories for the concurrent transfer of a first block of data between a first port and a first memory and a second block of data between a second port and a second memory, each of said memories having a capacity of a plurality of blocks of data.
Claim 2
Dependent Claim
102 words
A memory buffering system comprising: a plurality of memories; a plurality of data ports; multiplexing means for selectively coupling each of said data ports to each of said memories; and sequencing means, coupled to said multiplexing means, for providing control signals to said multiplexing means to alternately couple said data ports to each of said memories for the concurrent transfer of a first block of data between a first port and a first memory and a second block of data between a second port and a second memory, each of said memories having a capacity of a plurality of blocks of data.
Claim 3
Dependent Claim
47 words
The memory buffering system of claim 1 further comprising: a plurality of address bus inputs, one associated with each of said data ports; and multiplexing means for coupling each of said address bus inputs to one of said memories to which its corresponding data port is coupled.
Claim 4
Dependent Claim
21 words
The memory buffering system of claim 2 further comprising a separate address counter coupled to each of said address bus inputs.
Claim 5
Dependent Claim
32 words
The memory buffering system of claim 2 further comprising a number of bits of each said address bus sufficient to address said plurality of memories coupled as inputs to said sequencing means.
Claim 6
Dependent Claim
174 words
A memory buffering system comprising: a plurality of memories; a plurality of data ports; multiplexing means for selectively coupling each of said data ports to each of said memories; sequencing means, coupled to said multiplexing means, for providing control signals to said multiplexing means to alternately couple said data ports to each of said memories for the concurrent transfer of a first block of data between a first port and a first memory and a second block of data between a second port and a second memory, each of said memories having a capacity of a plurality of blocks of data; a plurality of address bus inputs, one associated with each of said data ports; multiplexing means for coupling each of said address bus inputs to one of said memories to which its corresponding data port is coupled; a separate address counter coupled to each of said address bus inputs; and a number of bits of each said address bus sufficient to address said plurality of memories coupled as inputs to said sequencing means.
Claim 7
Dependent Claim
174 words
A memory buffering system comprising: a plurality of memories; a plurality of data ports; multiplexing means for selectively coupling each of said data ports to each of said memories; sequencing means, coupled to said multiplexing means, for providing control signals to said multiplexing means to alternately couple said data ports to each of said memories for the concurrent transfer of a first block of data between a first port and a first memory and a second block of data between a second port and a second memory, each of said memories having a capacity of a plurality of blocks of data; a plurality of address bus inputs, one associated with each of said data ports; multiplexing means for coupling each of said address bus inputs to one of said memories to which its corresponding data port is coupled; a separate address counter coupled to each of said address bus inputs; and a number of bits of each said address bus sufficient to address said plurality of memories coupled as inputs to said sequencing means.
Claim 8
Independent Claim
97 words
A method for accessing a memory buffering system having a plurality of memories and a plurality of data ports, comprising the steps of: selectively coupling each of said data ports to each of said memories; alternately coupling said data ports to each of said memories for the transfer of a block of data, each of said memories having a capacity of a plurality of blocks of data; accessing data through the first port at the full bandwidth of the first port while simultaneously accessing data through the second port at the full capability of the second port.
Claim 9
Independent Claim
97 words
A method for accessing a memory buffering system having a plurality of memories and a plurality of data ports, comprising the steps of: selectively coupling each of said data ports to each of said memories; alternately coupling said data ports to each of said memories for the transfer of a block of data, each of said memories having a capacity of a plurality of blocks of data; accessing data through the first port at the full bandwidth of the first port while simultaneously accessing data through the second port at the full capability of the second port.
Claim 10
Dependent Claim
40 words
The method of claim 6 further comprising the step of coupling each of a plurality of address bus inputs, one associated with each of said data ports, to one of said memories to which its corresponding data port is coupled.
Claim 11
Dependent Claim
26 words
The memory buffering system of claim 1 wherein said sequencing means interleaves blocks of data from different ones of said ports in each of said memories.
Claim 12
Dependent Claim
26 words
The memory buffering system of claim 1 wherein said first port is coupled to a computer and said second port is coupled to a disk drive.
Claim 13
Dependent Claim
152 words
A disk drive buffer comprising: a plurality of buffer memories; a plurality of data ports, at least a first data port being coupled to a computer and at least a second data port being coupled to a disk drive; multiplexing means for selectively coupling each of said data ports to each of said buffer memories; a plurality of address ports associated with said data ports; and sequencing means, coupled to said multiplexing means, for providing control signals to said multiplexing means to interleave accesses by said ports between said memories by alternately coupling said data ports to each of said buffer memories in response to one or more bits from said address ports, each port being coupled to a single memory for only an access of a block of data at a time, each block of data being interleaved within one of said buffer memories between blocks of data from other ports.
Claim 14
Dependent Claim
152 words
A disk drive buffer comprising: a plurality of buffer memories; a plurality of data ports, at least a first data port being coupled to a computer and at least a second data port being coupled to a disk drive; multiplexing means for selectively coupling each of said data ports to each of said buffer memories; a plurality of address ports associated with said data ports; and sequencing means, coupled to said multiplexing means, for providing control signals to said multiplexing means to interleave accesses by said ports between said memories by alternately coupling said data ports to each of said buffer memories in response to one or more bits from said address ports, each port being coupled to a single memory for only an access of a block of data at a time, each block of data being interleaved within one of said buffer memories between blocks of data from other ports.
References Cited (Backward Citations)
US3303482A
Cited
GB1233087A
Cited
US3544777A
Cited
US3693159A
Cited
US3772652A
Cited
US3803560A
Cited
US3905023A
Cited
GB1497680A
Cited
US3917933A
Cited
US4070704A
Cited
US4093985A
Cited
US4207609A
Cited
US4342079A
Cited
US4339804A
Cited
US4467421A
Cited
JPS5688549A
Cited
JPS5694593A
Cited
JPS56163596A
Cited
JPS57111893A
Cited
JPS57111890A
Cited
JPS57169297A
Cited
JPS57195397A
Cited
US4507730A
Cited
JPS5883400A
Cited
US4468731A
Cited
US4464747A
Cited
US4825403A
Cited
JPS60156152A
Cited
US4817035A
Cited
US4849929A
Cited
US4667326A
Cited
US4814982A
Cited
US4768193A
Cited
US4722085A
Cited
US4761785A
Cited
US4761785B1
Cited
EP0266789A2
Cited
US4811296A
Cited
US4914656A
Cited
EP0369707A2
Cited
JPH06199999A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |