Multi-port register file with flow-through of data

Claim 1

A multiport RAM register file comprising: a. a read/write memory having a plurality of bit storage cells and a plurality of bit buses over which data may be written to or read from said bit storage cells, the number of bit buses being identified by the variable "n"; b. a plurality of input multiplexers, each having multiple inputs and an output, the number of such inputs corresponding to the number of input ports to be provided; c. each bit bus being connected to the output of a different one of the input multiplexers; d. each input of said multiplexers being connected to an input port, such that each multiplexer has an input connected to each of the input ports; e. flow-through address comparator means adapted to receive at least one write address and at least one read address, compare said read addresses and said write addresses, and, upon detecting a read address corresponding to a write address, enable an appropriate one of the input multiplexers to steer input data from a selected one of the input ports to an appropriate one of the bit busses; f. n-1 output multiplexers each having at least two inputs and a single output, with each input of each such output multiplexer being connected to a different one of said bit buses; g. a plurality of output ports, one output port being connected directly to one of said bit buses and each of the other output ports being connected to the output of one of the output multiplexers; h. read address comparator means for controlling the output multiplexers; and i. address decoder means operable in cooperation with the read/write memory to select addresses therein for reading and writing.