Data storage system with means for eliminating defective storage locations

Claim 2

In a data storage system in which a very large number of identical memory elements with complementary output signals are combined into an integrated memory matrix in such a manner that words with a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are unusable, the improvement comprising: each word in said memory matrix being provided with additional memory elements in excess of the said given number of bits with the number (n) of said additional memory elements per word being selected to correspond to the number of unusable memory elements to be expected for each word; each of said unusable memory elements being so modified that it causes a distinctive signal to be emitted when it is interrogated which identifies the unusability thereof; means for interrogating all of the memory elements of one word prior to writing information in said memory matrix and prior to reading information out of said memory matrix, and, switching means, responsive to said distinctive signals emitted during interrogation identifying an unusuable memory element in an addressed word, for causing that information associated with the V-th unusable memory element, where V 1,2 . . . n, n > OR = 1, to be stored in the V-th additional memory element during writing of a word into said memory matrix and for causing the information stored in the Vth additional memory element to be read out instead of the information furnished by the V-th unusable memory element during reading out of a word from said memory matrix.

Claim 3

The data storage system defined in claim 1 wherein said additional memory elements are provided in said memory matrix for each word spatially following the number of memory elements associated with said given number of bits.

Claim 4

The data storage system defined in claim 1 wherein said memory matrix is designed so that the error frequency of said additional memory elements is less than that of the memory elements of a word.

Claim 5

The data storage system defined in claim 1 wherein all of the first memory elements of all words are connected to common read and write lines, all of the second memory elements of all words are connected to respective common read and write lines, etc.; and wherein said switching means includes: a plurality of recognition circuit means, one for each of said common read and write lines, for recognizing an unusable memory element of the word being addressed; a plurality of first logic switching means, one for each of said common read and write lines, each of said first logic switching means being responsive to the output signals of the associated recognition circuit means and the associated memory element for interrupting or establishing, respectively, in dependence on whether or not an unusable memory element has been determined, the connection between said associated memory element and the associated input or output of said memory matrix; and, a second logic switching means responsive to the output signals from each of said recognition circuit means for establishing the connection between the input or output of said memory matrix associated with an unusable memory element and the associated additIonal memory element of the word being addressed.

Claim 6

The data storage system defined in claim 4 wherein: each of said memory elements is provided with a pair of read and write lines and said unusable memory elements have been modified so that they produce identical output signals on both of said pair of lines; each of said recognition circuit means is a respective first AND gate which is responsive to the outputs on both of said pair of lines; each of said first logic switching means is a respective second AND gate having one input connected to one of said pair of lines and a second negated input connected to the output of the respective said first AND gate, and an OR gate having one input connected to the output of the respective said second AND gate and its output connected to the associated input or output line for said memory matrix; and said second logic switching means includes a logic network means responsive to the output signals from each of said first AND gates for connecting the additional memory elements to an output line therefrom, and a plurality of third AND gates, each of which is associated with one of said recognition circuit means and one of said first logic switching means, each of said third AND gates having one input connected to an output line from said logic network means, a second input connected to the output of the associated first AND gate, and its output connected to a second input of the associated OR gate.

Claim 7

The data storage system defined in claim 5 wherein said memory matrix includes one additional memory element per word; and wherein said logic network means includes an OR gate having its inputs connected to the outputs of each of said first AND gates and its output connected to one input of a further AND gate, said further AND gate having its other input connected to the output of said additional memory element and its output connected to said second input of each of said third AND gates.

Claim 8

The data storage system defined in claim 5 wherein said memory matrix includes a plurality of said additional memory elements per word, and wherein said logic network means has a plurality of output lines, each of said output lines being connected to said second input of a different one of said third AND gates, a first plurality of input lines connected to the respective outputs of said first AND gates, and a second plurality of input lines connected to the outputs of the respective additional memory elements, said logic network means being responsive to a signal on one of said first plurality of input lines indicating an unusable memory element for connecting the output of the associated one of said additional memory elements to the corresponding one of said plurality of output lines.

Claim 9

The data storage system defined in claim 1 wherein said switching means includes: a separate recognition circuit means for determining the usability of a memory element for each bit location of the word, means responsive to an output signal from said recognition circuit means indicating an unusable memory element for blocking the input of writing signals to the associated bit location; and further means responsive to said output signal from said recognition circuit means for conducting the writing signals to the associated additional memory element for storage therein.

Claim 10

The data storage system defined in claim 1 wherein at least a portion of the words of said memory matrix are divided into partial words, all in the same manner so that the number of the usable memory elements to be expected in each partial word does not exceed a certain number; wherein a number (n) of additional memory cells is provided for each partial word which number corresponds to the number of unusable memory cells to be expected; and wherein a plurality of said switching means are provided, one for each partial word so as to cause the additional memory elements of each partial word to be used instead of the unusable elements of each partial word.

Claim 11

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix so that words having a given number of bits are stored, and wherein due to the manufacturing process employed, a portion of said memory elements are normally unusable and accordingly additional memory elements are provided for each word in excess of the given number of bits with the numer of said additional memory elements being selected to correspond to the number of unusable memory elements to be expected for said word, the improvement comprising: said memory elements being of the type which can be read out without the destruction of the contents thereof; each of said unusable memory elements being modified in such a manner that it emits a signal during interrogation which identifies the unusability of the memory element; a logic network means connected to the output lines of said memory matrix for detecting and evaluating the output signals from said memory elements during interrogation thereof to identify the position of the defective unusable memory elements; a switching means responsive to the output signals from said logic network means for storing those bits of a word which are to be stored in an unusable memory element in the next-following usable memory element of the word during writing in of information to the memory; means for supply a word selection pulse to the respective memory elements of a word to interrogate said memory elements and effect a read out thereof prior to writing of information therein in order to determine the presence of defective and unusable memory elements, said word selection pulse having a duration which is sufficiently long so that during said duration said logic network means can effect the necessary linkages and said switching means can effect the necessary connections to cause write-in of the information into only usable memory elements.

Claim 12

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix so that words having a given number of bits are stored, and wherein due to the manufacturing process employed, a portion of said memory elements are normally unusable and accordingly additional memory elements are provided for each word in excess of the given number of bits with the numer of said additional memory elements being selected to correspond to the number of unusable memory elements to be expected for said word, the improvement comprising: said memory elements being of the type which can be read out without the destruction of the contents thereof; each of said unusable memory elements being modified in such a manner that it emits a signal during interrogation which identifies the unusability of the memory element; a logic network means connected to the output lines of said memory matrix for detecting and evaluating the output signals from said memory elements during interrogation thereof to identify the position of the defective unusable memory elements; a switching means responsive to the output signals from said logic network means for storing those bits of a word which are to be stored in an unusable memory element in the next-following usable memory element of the word during writing in of information to the memory; means for supply a word selection pulse to the respective memory elements of a word to interrogate said memory elements and effect a read out thereof prior to writing of information therein in order to determine the presence of defective and unusable memory elements, said word selection pulse having a duration which is sufficiently long so that during said duration said logic network means can effect the necessary linkages and said switching means can effect the necessary connections to cause write-in of the information into only usable memory elements.

Claim 13

The data storage system defined in claim 10 further including control means responsive to the signals emitted by said memory elements of a word during interrogation for effecting a decreased travel time of data from or to said memory elements when the detected signals indicate that the particular word of the memory being read does not contain any unusable memory elements and hence switching to one of the additional memory elements is not required.

Claim 14

The data storage system defined in claim 11 wherein said means for supplying said word selection pulse can furnish word selection pulses of at least two different durations, one of which is shorter than said duration of said word selection pulse; and wherein said means for supplying said word selection pulse is responsive to the output signal from said control means to provide the word selection pulse of shorter duration when the output of said control means indicates the absence of unusable memory elements in the interrogated word.