US4918587A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Prefetch circuit for a computer memory subject to consecutive addressing
Assignee: Teradata US Inc
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Filing: 1987-12-11
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Granted: 1990-04-17
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Expires: 2007-12-11
Abstract
Abstract A computer memory prefetch architecture for accelerating the rate at which data can be accessed from memory and transmitted to a processor when successive addresses are numerically consecutive. Upon the identification of a consecutive address sequence, the succession of real addresses are generated directly by a counter. The memory of the computer system is partitioned into odd and even banks which are selectively addressed using the odd and even segments of the address generated in the counter. Output data from each memory bank is stored in a corresponding register operable to transmit the data entered therein during a previous memory address cycle while the anticipated next address data is written into the other register. The prefetch architecture may be meaningfully used to accelerate the access rate of a memory shared by multiple processors.
Inventors
- 👤 Richard G. Pechter
- 👤 Ronald Selkovitch
- 👤 Quoanh W. Tsy
- 👤 William C. Woolf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:21
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0607
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
191 words
An apparatus for accelerating the rate that consecutively addressed data in a partitioned computer memory is furnished to a processor in the computer, comprising: an addressable memory array having an even address bank and an odd address bank; a processor bus; an address latch connecting the processor bus to both the even and the odd banks of the memory array; means connected between said latch and said address banks for receiving a first address from said latch and for consecutively indexing said first address to consecutively address the even and odd banks of the memory array; an even transceiver register connected between the even bank of the memory array and the processor bus; an odd transceiver register connected between the odd bank of the memory array and the processor bus; and means responsive to a consecutive addressing command signal from the processor for enabling a first of said registers to provide data to the processor bus in time coincidence with addressing, by said indexing means, the memory array bank corresponding to a second of said registers and for enabling said second register to latch data from such corresponding memory array bank.
Claim 2
Independent Claim
191 words
An apparatus for accelerating the rate that consecutively addressed data in a partitioned computer memory is furnished to a processor in the computer, comprising: an addressable memory array having an even address bank and an odd address bank; a processor bus; an address latch connecting the processor bus to both the even and the odd banks of the memory array; means connected between said latch and said address banks for receiving a first address from said latch and for consecutively indexing said first address to consecutively address the even and odd banks of the memory array; an even transceiver register connected between the even bank of the memory array and the processor bus; an odd transceiver register connected between the odd bank of the memory array and the processor bus; and means responsive to a consecutive addressing command signal from the processor for enabling a first of said registers to provide data to the processor bus in time coincidence with addressing, by said indexing means, the memory array bank corresponding to a second of said registers and for enabling said second register to latch data from such corresponding memory array bank.
Claim 3
Dependent Claim
73 words
The apparatus recited in claim 1, wherein the means for enabling includes: means for transmitting data directly from one bank of the memory array to the processor bus and from the other bank of the memory array to the corresponding data register, in response to said first address from said latch received by one of said memory banks in time coincidence with a compensated address received by the other of said memory banks.
Claim 4
Dependent Claim
28 words
The apparatus recited in claim 2, wherein the means for consecutively indexing address data is an address counter, connected selectively to address either bank of the memory array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-16 | 1993-10-16 | 1994-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-16 | 1997-10-16 | 1998-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-16 | 2001-10-16 | 2002-04-17 | $7700.00 | Window Closed / Lapsed |