Memory control structure for a pipelined mini-processor system

Claim 1

In a word processing system including a pipelined processor having an input bus, a system clock, and an output bus, and including a plurality of random access memory blocks and a plurality of read only storage memory blocks, said random access memory blocks and said read only storage memory blocks having different operating characteristics, a memory control system interconnected to said processor and said memory blocks for controlling access to the memory blocks by the processor, wherein the memory control system comprises: means for receiving clock signals from said processor; means responsive to said clock signals for generating memory cycle timing signals having a plurality of frequencies required to operate said memory blocks; means for receiving an address and an instruction from said processor; decoding means responsive to said address and instruction for generating and applying power selection signals and one of said memory cycle timing signals only to the memory block which contains the address equivalent to the address received from said processor; and sampling means for latching the output of the selected memory block onto the input bus to the processor concurrent with the receipt of the next address and instruction from the processor.