Memory overlay system

Claim 2

A memory system comprising: A. a first memory having a plurality of storage locations; B. a second memory having a plurality of storage locations, addresses of each of said locations of said second memory corresponding toa ddresses of said first memory storage locations, said second memory comprising a plurality of segments, each of said segments having a plurality of storage locations, wherein the number of storage locations in said first memory is equal to the number of storage locations in one of said segments; C. means for selecting one of said segments of said second memory; D. means for simultaneously addressing both said first memory and the selected segment of said second memory; and E. a control memory for indicating whether the storage locations of said first memory of the selected segment of said second memory are to be utilized when both said first memory and the selected segment of said second memory are addressed.

Claim 3

A system as defined in claim 1 wherein said control memory is addressed concurrently with the first and second memories.

Claim 4

A system as defined in claim 2, further comprising means for disabling said first memory so that only said second memory is responsive to the addressing of both said first and second memories.

Claim 5

A system as defined in claim 2, further comprising means for disabling said second memory so that only said first memory is responsive to the addressing of both said first and second memories.

Claim 6

A memory system comprising: A. a first memory having a plurality of storage locations; B. a second memory having a plurality of storage locations, addresses of each of said locations of said second memory corresponding to addresses of said first memOry storage locations, said second memory comprising a plurality of segments, each of said segments having a plurality of storage locations, wherein the number of storage locations in said first memory is less than the number of storage locations in one of said segments; C. means for selecting one of said segments of said second memory; D. means for simultaneously addressing both said first memory and the selected segment of said second memory; E. a control memory for indicating whether the storage locations of said first memory or of said second memory are to be utilized; and F. means for inhibiting the utilization of said first memory when said means for addressing is addressing a predetermined portion of said selected segment.

Claim 7

A memory system comprising: A. a first memory having a plurality of storage locations; B. a second memory having a plurality of storage locations, addresses of each of said locations of said second memory corresponding to addresses of said first memOry storage locations, said second memory comprising a plurality of segments, each of said segments having a plurality of storage locations, wherein the number of storage locations in said first memory is less than the number of storage locations in one of said segments; C. means for selecting one of said segments of said second memory; D. means for simultaneously addressing both said first memory and the selected segment of said second memory; E. a control memory for indicating whether the storage locations of said first memory or of said second memory are to be utilized; and F. means for inhibiting the utilization of said first memory when said means for addressing is addressing a predetermined portion of said selected segment.

Claim 8

A system as defined in claim 5 wherein said control memory is addressed concurrently with said first and second memories.

Claim 9

A memory system comprising: A. a first memory having a plurality of word storage locations, each of said word storage locations having a plurality of bit storage locations; B. a second memory having a plurality of word storage locations, each of said word storage locations having a plurality of bit storage locations; C. a control memory having a plurality of bit storage locations, wherein the number of said bit storage locations in said control memory is equal to the number of word storage locations in said first memory, each of said bit storage locations in said control memory indicating either a first binary state or a second binary state; D. means for substantially simultaneously addressing the word storage locations of said first and second memories and the bit storage locations of said control memory, said means for addressing including means for providing corresponding identical representations of each of said locations in each of said memories; E. means for enabling the utilization of the addressed word storage location in said first memory when the addressed bit storage location of said control memory indicates said first binary state; nd F. means for enabling the utiliztion of the addressed word storage location in said second memory when the addressed bit storage location of said control memory indicates said second binary state.

Claim 10

A memory system comprising: A. a first memory having a plurality of word storage locations, each of said word storage locations having a plurality of bit storage locations; B. a second memory having a plurality of word storage locations, each of said word storage locations having a plurality of bit storage locations; C. a control memory having a plurality of bit storage locations, wherein the number of said bit storage locations in said control memory is equal to the number of word storage locations in said first memory, each of said bit storage locations in said control memory indicating either a first binary state or a second binary state; D. means for substantially simultaneously addressing the word storage locations of said first and second memories and the bit storage locations of said control memory, said means for addressing including means for providing corresponding identical representations of each of said locations in each of said memories; E. means for enabling the utilization of the addressed word storage location in said first memory when the addressed bit storage location of said control memory indicates said first binary state; nd F. means for enabling the utiliztion of the addressed word storage location in said second memory when the addressed bit storage location of said control memory indicates said second binary state.

Claim 11

A system as defined in claim 7 further comprising: A. means for generating a first signal; B. gate means responsive to said first signal, said gate means coupled to said control memory; and wherein C. said first memory is inhibited from being utilized in response to said first signal regardless of the binary state indicated by the addressed bit storage location of said control memory.

Claim 12

A system as defined in claim 8 further comprising: A. means for generating a second signal; B. means for coupling said gate means for response to said second signal; and wherein C. said second memory is inhibited from being utilized in response to said second signal regardless of the binary state indicated by the addressed bit storage location of said control memory.

Claim 13

A system as defined in claim 7 wherein said first memory is a read only memory and wherein said second memory is the main memory of a data processor.

Claim 14

A system as defined in claim 7 wherein the number of word storage locations in said first memory is equal to the number of word storage locations in said second memory.

Claim 15

A system as defined in claim 7 wherein: A. said second memory includes a plurality of segments, each of said segments including a plurality of word storage locations equal in number to the number of word storage locations in said first memory; and further comprising: B. means for selecting one of said segments; C. means for designating the one of said segments which is to be simultaneously addressed with said first memory by said means for addressing; and D. means for enabling said first memory for utilization as indicated by said control memory when said sElected segment and said designated segment are the same.

Claim 16

A system as defined in claim 7 wherein: A. the number of word storage locations in said first memory is less than the number of word storage locations in said second memory; and further comprising: B. means for inhibiting the utilization of said first memory when said means for addressing is addressing a predetermined portion of said second memory.

Claim 17

A system as defined in claim 7 wherein: A. the number of word storage locations in said first memory is one half of the number of word storage locations in said second memory; and further comprising: B. means for inhibiting the utilization of said first memory when a first half of said second memory is addressed; and C. means for enabling the utilization of said first memory as indicated by said control memory when a second half of said second memory is addressed.

Claim 18

A system as defined in claim 7 wherein the address provided by said means for addressing is the address of a location in said second memory.