Information processing unit

Claim 2

An information processing unit comprising: a memory device which stores a data word at a standard memory address; with each standard memory address specifying several memory areas in which to store said data word and wherein each of said several memory areas is identified by an internal address; a central processing unit which accesses said data word stored in said memory device by sending said standard memory address to an address control device; said address control device, coupled to said central processing unit, stores said internal address and combines said internal address with said standard address to form a compound address specifying a given one of said several memory areas in which said data word is stored; an error detection device, coupled to said memory device and said address control device, which generates an error signal if the data word read from said memory device contains an error; said address control device having an internal address update device which, upon receipt of said error signal, prevents the use of the given memory area used to store said error containing data word by selecting a new internal address, and wherein said address control device forms a new compound address.

Claim 3

An information processing unit comprising: a memory device which stores a data word at a standard memory address; with each standard memory address specifying several memory areas in which to store said data word and wherein each of said several memory areas is identified by an internal address; a central processing unit which accesses said data word stored in said memory device by sending a standard memory address to an address control device; said address control device, coupled to said central processing unit, stores said internal address and combines said internal address with said standard address to form a compound address specifying a given one of said several memory areas in which said data word is stored; an error detection device, coupled to said memory device and said address control device, which generates an error signal if the data word read from said memory device contains an error; said address control device having an internal address update device which, upon receipt of said error signal, prevents the use of the given memory area used to store said error containing data word by selecting a new internal address, and wherein said address control device forms a new compound address; and an error correction device, coupled to said error detection device, which, corrects errors in a data word read from said memory device, according to said error signals.

Claim 4

An information processing unit comprising: a memory device which stores a data word at a standard memory address; with each standard memory address specifying several memory areas in which to store said data word and wherein each of said several memory areas is identified by an internal address; a central processing unit which accesses said data word stored in said memory device by sending a standard memory address to an address control device; said address control device, coupled to said central processing unit, stores said internal address and combines said internal address with said standard address to form a compound address specifying a given one of said several memory areas in which said data word is stored; an error detection device, coupled to said memory device and said address control device, which generates an error signal if the data word read from said memory device contains an error; said address control device having an internal address update device which, upon receipt of said error signal, prevents the use of the given memory area used to store said error containing data word by selecting a new internal address, and wherein said address control device forms a new compound address; and an error correction device, coupled to said error detection device, which, corrects errors in a data word read from said memory device, according to said error signals.

Claim 5

An address control device in an information processor, having a central processing unit, an error detection device and a memory for storing data words comprising: an internal address device which stores an internal address designating which one of a set of memory areas associated with a standard memory address contains a given data word; an internal address update device which writes a new internal address to said internal address device when said internal address update device receives an error signal from said error detection device indicating that said given data word read from said memory contains an error; and a compound address device which combines said internal address stored in said internal address memory device with a standard address received from the central processing unit of said information processor to form a compound address which designates a given memory area containing said given data word.

Claim 6

An address control device in an information processor, having a central processing unit, an error detection device and a memory for storing data words comprising: an internal address device which stores an internal address designating which one of a set of memory areas associated with a standard memory address contains a given data word; an internal address update device which writes a new internal address to said internal address device when said internal address update device receives an error signal from said error detection device indicating that said given data word read from said memory contains an error; and a compound address device which combines said internal address stored in said internal address memory device with a standard address received from the central processing unit of said information processor to form a compound address which designates a given memory area containing said given data word.