Apparatus for automatically correcting erroneous data and for storing the corrected data in a common pool alternate memory array

Claim 1

A microprocessor controlled apparatus for reading data from a main memory means, for detecting the existence of a double bit error in said data, for correcting said double bit error without the use of spare memory chips, and for ensuring that said error will not be reproduced during a subsequent read of said data, comprising: said main memory means for storing said data therein, said data including erroneous and non-erroneous data; detection means, connected to said main memory means, for detecting the existence of a double bit error in said data read from said main memory means; first correction means, connected to said microprocessor, for correcting a single bit error of said double bit error detected by said detection means thereby producing partially corrected data and for developing an output signal indicative of said partially corrected data; common pool alternate memory array means, connected to said detection means and responsive to said output signal developed from said first correction means, for storing said partially corrected data, received from said first correction means, said partially corrected data being simultaneously accessed from said common pool alternate memory array means when said data is accessed from said main memory means, thereby changing said double bit error into a remaining single bit error; and second correction means, connected to said detection means, for correcting said remaining single bit error.