High performance burst read data transfer operation

Claim 1

A system comprising: a clock generator for generating a single frequency clock reference signal for synchronizing operations within said system using predetermined transitions of said reference signal; a unit coupled to said clock generator for generating commands for reading and writing memory, one of said commands specifying a burst operation; a synchronous bus having address, command and data sections and operating according to a predetermined bus protocol; and, a memory tightly coupled to said unit through said synchronous bus, said memory comprising: a pair of dynamic random access (DRAM) memories coupled to said bus, each of said DRAMs having an identical width, the sum of the widths being no more than twice as wide as said data section of said bus; and, control logic circuit means coupled to said DRAM memories and to said clock generator, said control logic circuit means including: first circuit means for generating a column address timing signal in response to selected ones of said predetermined transitions of said clock reference signal which provides an interval which is sufficient in duration to perform a plurality of successive read cycles of operation in said DRAM memories; second circuit means for generating a blipper pulse signal in response to two successive transitions other than said predetermined transitions; and, logic circuit means coupled to said first and second circuit means for combining said column address timing signal and said blipper pulse signal to produce a column address strobe (CAS) signal to be applied to said DRAM memories during said successive read cycles of operation for reading out a plurality of successive pairs of words for completing the execution of said burst operation without incurring any unit wait states.

Claim 2

A system comprising: a clock generator for generating a single frequency clock reference signal for synchronizing operations within said system using predetermined transitions of said reference signal; a unit coupled to said clock generator for generating commands for reading and writing memory, one of said commands specifying a burst operation; a synchronous bus having address, command and data sections and operating according to a predetermined bus protocol; and, a memory tightly coupled to said unit through said synchronous bus, said memory comprising: a pair of dynamic random access (DRAM) memories coupled to said bus, each of said DRAMs having an identical width, the sum of the widths being no more than twice as wide as said data section of said bus; and, control logic circuit means coupled to said DRAM memories and to said clock generator, said control logic circuit means including: first circuit means for generating a column address timing signal in response to selected ones of said predetermined transitions of said clock reference signal which provides an interval which is sufficient in duration to perform a plurality of successive read cycles of operation in said DRAM memories; second circuit means for generating a blipper pulse signal in response to two successive transitions other than said predetermined transitions; and, logic circuit means coupled to said first and second circuit means for combining said column address timing signal and said blipper pulse signal to produce a column address strobe (CAS) signal to be applied to said DRAM memories during said successive read cycles of operation for reading out a plurality of successive pairs of words for completing the execution of said burst operation without incurring any unit wait states.