US5841580A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit I/O using a high performance bus interface
Assignee: Rambus Inc
•
Filing: 1997-02-10
•
Granted: 1998-11-24
•
Expires: 2017-02-10
Abstract
Abstract The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
Inventors
- 👤 Michael Farmwald
- 👤 Mark Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:01
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F11/00; G06F11/006; G06F12/00; G06F12/02; G06F12/0215; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1668; G06F13/1678; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368; G06F13/376; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C29/00; G11C29/70; G11C29/88; G11C5/00; G11C5/02; G11C5/04; G11C5/06; G11C5/063; G11C5/066; G11C7/1006; G11C7/1012; G11C7/1015; G11C7/1045; G11C7/1057; G11C7/1069; G11C7/1072; G11C7/1078; G11C7/1084; G11C7/22; G11C7/222; G11C7/225; G11C8/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/108; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
81 words
A computer system comprising: a bus; a semiconductor device coupled to the bus, the semiconductor device comprising an access-time register operative to store a value indicative of a delay time for the semiconductor device to respond to a bus transaction request; and a bus master coupled to the bus, the bus master transmitting the value and the bus transaction request to the semiconductor device via the bus, wherein the semiconductor device responds to the bus transaction request after the delay time.
Claim 2
Dependent Claim
81 words
A computer system comprising: a bus; a semiconductor device coupled to the bus, the semiconductor device comprising an access-time register operative to store a value indicative of a delay time for the semiconductor device to respond to a bus transaction request; and a bus master coupled to the bus, the bus master transmitting the value and the bus transaction request to the semiconductor device via the bus, wherein the semiconductor device responds to the bus transaction request after the delay time.
Claim 3
Dependent Claim
35 words
The computer system of claim 1, wherein the delay time is selected from a set of delay times such that the semiconductor device responds to the bus transaction request after a predetermined period of time.
Claim 4
Dependent Claim
76 words
A semiconductor device receiving a bus transaction request from a bus, the semiconductor device comprising: a plurality of conductors coupling the semiconductor device to the bus to receive the bus transaction request; and interface circuitry coupled to the plurality of conductors and including at least one access-time register operative to store a value indicative of a delay time for the semiconductor device, wherein the semiconductor device responds to the bus transaction request after the delay time.
Claim 5
Dependent Claim
76 words
A semiconductor device receiving a bus transaction request from a bus, the semiconductor device comprising: a plurality of conductors coupling the semiconductor device to the bus to receive the bus transaction request; and interface circuitry coupled to the plurality of conductors and including at least one access-time register operative to store a value indicative of a delay time for the semiconductor device, wherein the semiconductor device responds to the bus transaction request after the delay time.
Claim 6
Dependent Claim
14 words
The semiconductor device of claim 3, wherein the semiconductor device is a memory device.
Claim 7
Dependent Claim
35 words
The semiconductor device of claim 3, wherein the delay time is selected from a set of delay times such that the semiconductor device responds to the bus transaction request after a predetermined period of time.
Claim 8
Independent Claim
45 words
A method for programming a semiconductor device, comprising: writing a value to an access-time register of the semiconductor device, the value specifying a delay time for the semiconductor device; receiving a bus transaction request; and responding to the bus transaction request after the delay time.
Claim 9
Independent Claim
45 words
A method for programming a semiconductor device, comprising: writing a value to an access-time register of the semiconductor device, the value specifying a delay time for the semiconductor device; receiving a bus transaction request; and responding to the bus transaction request after the delay time.
Claim 10
Dependent Claim
13 words
The method of claim 6, wherein the semiconductor device is a memory device.
Claim 11
Dependent Claim
89 words
A memory device, comprising: an array of memory cells connected in rows and columns; a plurality of conductors for coupling to an external bus and for carrying address information and data information; and interface circuitry coupled to the plurality of conductors and the array of memory cells for accessing the array of memory cells in response to the address information received from the plurality of conductors, the interface circuitry including an access-time register for storing the data information that defines an access time of the array of memory cells.
Claim 12
Dependent Claim
89 words
A memory device, comprising: an array of memory cells connected in rows and columns; a plurality of conductors for coupling to an external bus and for carrying address information and data information; and interface circuitry coupled to the plurality of conductors and the array of memory cells for accessing the array of memory cells in response to the address information received from the plurality of conductors, the interface circuitry including an access-time register for storing the data information that defines an access time of the array of memory cells.
Claim 13
Dependent Claim
41 words
The memory device of claim 8, wherein the interface circuitry comprises a plurality of registers including a plurality of access-time registers, and wherein the plurality of conductors carries control information for selecting the access-time register from the plurality of access-time registers.
Claim 14
Dependent Claim
68 words
The memory device of claim 8, wherein address information specifying the access-time register and control information specifying an access-time register operation are received from the plurality of conductors, wherein the data information that defines the access time of the array of memory cells is loaded into the access-time register from the plurality of conductors in response to the address and control information received for the access-time register operation.
Claim 15
Dependent Claim
18 words
The memory device of claim 8, wherein the memory device is a dynamic random access memory device (DRAM).
Claim 16
Dependent Claim
32 words
The memory device of claim 8, wherein the memory device waits a time equal to the access time before accepting data for the array of memory cells from the plurality of conductors.
Claim 17
Dependent Claim
32 words
The memory device of claim 8, wherein the memory device waits a time equal to the access time before supplying data from the array of memory cells to the plurality of conductors.
Claim 18
Dependent Claim
60 words
A memory device comprising: at least one memory section; and a device interface coupling the memory section to a bus, the device interface receiving a bus transaction request from the bus, the device interface comprising at least one register including an access-time register whose contents indicate a delay time after which the memory device responds to the bus transaction request.
Claim 19
Dependent Claim
60 words
A memory device comprising: at least one memory section; and a device interface coupling the memory section to a bus, the device interface receiving a bus transaction request from the bus, the device interface comprising at least one register including an access-time register whose contents indicate a delay time after which the memory device responds to the bus transaction request.
Claim 20
Dependent Claim
39 words
The memory device of claim 14, wherein the transaction request information includes control information specifying a particular access-time register within the memory device for determining the delay time at which the memory device responds to the bus transaction request.
Claim 21
Dependent Claim
28 words
The memory device of claim 14, wherein the memory section is a dynamic memory section and the delay time is at least a row address strobe access time.
Claim 22
Dependent Claim
26 words
The memory device of claim 14, wherein the memory section is a dynamic memory section and the delay time is at least a page-mode access time.
Claim 23
Dependent Claim
26 words
The memory device of claim 14, wherein the memory section is a dynamic memory section and the delay time is at least a normal-mode access time.
Claim 24
Dependent Claim
23 words
The memory device of claim 14, wherein the delay time is a fixed number of cycles for accessing the at least one register.
Claim 25
Dependent Claim
14 words
The memory device of claim 19, wherein the fixed number of cycles is eight.
Claim 26
Dependent Claim
35 words
The memory device of claim 14, wherein the delay time is selected from a set of delay times such that the semiconductor device responds to the bus transaction request after a predetermined period of time.
Claim 27
Independent Claim
155 words
A system comprising: a bus; a first memory device comprising: a first memory section; a first device interface coupling the first memory section to the bus, the first device interface receiving a first bus transaction request from the bus, the first device interface including a first access-time register whose contents indicate a first delay time after which the first memory device responds to the first bus transaction request; and a second memory device comprising: a second memory section; a second device interface coupling the second memory section to the bus, the second device interface receiving a second bus transaction request from the bus, the second device interface including a second access-time register whose contents indicate a second delay time after which the second memory device responds to the second bus transaction request, wherein the first memory device is capable of transferring information on the bus during the second delay time of the second memory device.
Claim 28
Independent Claim
155 words
A system comprising: a bus; a first memory device comprising: a first memory section; a first device interface coupling the first memory section to the bus, the first device interface receiving a first bus transaction request from the bus, the first device interface including a first access-time register whose contents indicate a first delay time after which the first memory device responds to the first bus transaction request; and a second memory device comprising: a second memory section; a second device interface coupling the second memory section to the bus, the second device interface receiving a second bus transaction request from the bus, the second device interface including a second access-time register whose contents indicate a second delay time after which the second memory device responds to the second bus transaction request, wherein the first memory device is capable of transferring information on the bus during the second delay time of the second memory device.
References Cited (Backward Citations)
US3633166A
Cited
US3691534A
Cited
US3740723A
Cited
US3924241A
Cited
US3821715A
Cited
US3983537A
Cited
US3975714A
Cited
US3972028A
Cited
US3882470A
Cited
US3969706A
Cited
US4263650A
Cited
US4263650B1
Cited
US4007452A
Cited
US4494186A
Cited
US4375665A
Cited
US4234934A
Cited
US4315308A
Cited
US4354258A
Cited
US4286321A
Cited
US4443864A
Cited
US4306298A
Cited
US4468738A
Cited
US4385350A
Cited
US4945471A
Cited
US4493021A
Cited
US4630193A
Cited
US4513374A
Cited
US4811202A
Cited
US4481625A
Cited
US4595923A
Cited
US4480307A
Cited
US4488218A
Cited
US4449207A
Cited
US4761799A
Cited
US4513370A
Cited
US4608700A
Cited
US4562435A
Cited
US4571672A
Cited
US4570220A
Cited
US4882669A
Cited
US4635192A
Cited
US4660141A
Cited
US4745548A
Cited
US4654655A
Cited
US4766536A
Cited
US4775931A
Cited
US4566098A
Cited
US4649516A
Cited
US4758993A
Cited
US4675813A
Cited
US4860198A
Cited
US4933835A
Cited
US4862158A
Cited
US4757473A
Cited
US4748320A
Cited
US4779089A
Cited
US4858112A
Cited
US4965792A
Cited
US4785396A
Cited
US4803621A
Cited
US4785394A
Cited
US5117494A
Cited
US5056060A
Cited
US5038320A
Cited
US4837682A
Cited
US4937733A
Cited
US5040153A
Cited
US4947484A
Cited
US4920486A
Cited
US5093807A
Cited
US4954992A
Cited
US5083260A
Cited
US5193199A
Cited
US5220673A
Cited
US5111423A
Cited
US5038317A
Cited
US5247518A
Cited
US5018110A
Cited
US5063561A
Cited
US5251309A
Cited
US4982400A
Cited
US5129069A
Cited
US5193149A
Cited
US4940909A
Cited
US5452420A
Cited
US5083296A
Cited
US4970418A
Cited
US5121382A
Cited
US5317723A
Cited
US5179670A
Cited
US5111464A
Cited
US5175831A
Cited
US5371892A
Cited
US5012408A
Cited
US5301155A
Cited
US5226009A
Cited
US5606717A
Cited
US5270973A
Cited
US5077693A
Cited
US5276641A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |