US5012408A
Expired / Lapsed
US
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Memory array addressing system for computer systems with multiple memory arrays
Assignee: Hewlett Packard Development Co LP
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Filing: 1990-03-15
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Granted: 1991-04-30
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Expires: 2010-03-15
Abstract
Abstract A computer system has a set of memory module slots, each of which may receive a memory module or may be left empty. The memory slots are arranged to accept at least two different types of memory modules having different amounts of memory storage. Each type of memory module generates a module type signal which denotes the type of the module and thus the amount of memory storage in the module. Whenever the system is powered on or reset, the system's memory initialization software analyzes the module type signals generated by the memory modules which are installed in memory slots. Each memory module is assigned a physical address range based solely on the size of the memory module and the slot in which it is located, regardless of what other memory modules are being used. The computer system thereby determines which portions of the computer's address space will be used for primary memory. The computer system is a multitasking computer system which has a virtual memory management system. Once the addresses occupied by memory modules have been identified, the primary memory is divided into a set of pages. The usage of these pages are governed by the computer system's virtual memory management system, which guarantees that all memory references to primary memory will reference only addresses in the aforementioned set of pages.
Inventors
- 👤 David G. Conroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:40
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0684; G06F12/08; G06F12/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
288 words
A computer memory system, comprising: address bus means for transmitting sets of address signals, each set of address signals defining an address in a predefined address space; a plurality of memory module slot means, coupled to said address bus means, for receiving memory modules; each memory module slot means including means for receiving a corresponding memory module enable signal; at least one of said memory module slot means including means for receiving at least two different types of memory modules having differing amounts of memory storage; memory management means, coupled to said plurality of memory module slot means, for assigning an address range to each memory module slot means solely on the basis of a type of memory module, if any, inserted therein, each said assigned address range being independent of which type of memory modules, if any, are inserted in other ones of said memory module slot means; and decoder means coupled to said address bus means and said plurality of memory module slot means, for decoding each said set of address signals, and for generating a memory module enable signal corresponding to one of said memory module slot means whenever said set of address signals define an address in one of said predefined address ranges assigned to said plurality of memory module slot means; wherein each said memory module slot means has a fixed, predefined address range assigned thereto for each different type of memory module which it has means for receiving, and said assigned address ranges for memory module slot means with memory modules inserted therein need not be contiguous; whereby memory modules can be inserted in any selected ones of said memory module slot means without regard to the corresponding address ranges assigned thereto.
Claim 2
Dependent Claim
288 words
A computer memory system, comprising: address bus means for transmitting sets of address signals, each set of address signals defining an address in a predefined address space; a plurality of memory module slot means, coupled to said address bus means, for receiving memory modules; each memory module slot means including means for receiving a corresponding memory module enable signal; at least one of said memory module slot means including means for receiving at least two different types of memory modules having differing amounts of memory storage; memory management means, coupled to said plurality of memory module slot means, for assigning an address range to each memory module slot means solely on the basis of a type of memory module, if any, inserted therein, each said assigned address range being independent of which type of memory modules, if any, are inserted in other ones of said memory module slot means; and decoder means coupled to said address bus means and said plurality of memory module slot means, for decoding each said set of address signals, and for generating a memory module enable signal corresponding to one of said memory module slot means whenever said set of address signals define an address in one of said predefined address ranges assigned to said plurality of memory module slot means; wherein each said memory module slot means has a fixed, predefined address range assigned thereto for each different type of memory module which it has means for receiving, and said assigned address ranges for memory module slot means with memory modules inserted therein need not be contiguous; whereby memory modules can be inserted in any selected ones of said memory module slot means without regard to the corresponding address ranges assigned thereto.
Claim 3
Dependent Claim
25 words
The computer memory system set forth in claim 1, further including at least one memory module inserted into one of said memory module slot means.
Claim 4
Dependent Claim
82 words
The computer memory system set forth in claim 1, further including: at least one memory module, each memory module inserted into one of said memory module slot means and each including means for generating a module type signal denoting the type of said memory module and amount of memory storage in said memory module; said memory management means receiving said module type signal for each said memory module, and determining the predefined address range corresponding to said at least one memory module.
Claim 5
Dependent Claim
129 words
The computer memory system set forth in claim 1, further including: at least one memory module, each memory module inserted into one of said memory module slot means and each including means for generating a module type signal denoting the type of said memory module and amount of memory storage in said memory module; each said memory module storing data at specified memory locations within said predefined address range assigned to said memory module slot to which said memory module is coupled; said memory management means receiving said module type signal for each said memory module, determining the predefined address range corresponding to said at least one memory module, and enabling access only to memory locations within said predefined address ranges corresponding to said at least one memory module.
Claim 6
Dependent Claim
160 words
The computer memory system set forth in claim 1, further including; at least one memory module, each memory module inserted into one of said memory module slot means and each including means for generating a module type signal denoting the type of said memory module and amount of memory storage in said memory module; each said memory module storing data at specified memory locations within said predefined address range assigned to said memory module slot to which said memory module is coupled; said memory management means receiving said module type signal for each said memory module, determined a predefined address range corresponding to said at least one memory module, denoting lists of pages of predetermined size within each of said predefined address ranges corresponding to said at least one memory module, and enabling access only to memory locations within said pages denoted in said lists; whereby said memory management means prevents access to memory locations not occupied by memory modules.
Claim 7
Independent Claim
270 words
A method of accessing data storage locations in a computer memory system, said computer memory system including an address bus for transmitting sets of address signals, each set of address signals defining an address in a predefined address space, and a plurality of memory module slots, coupled to said address bus, with memory modules inserted in at least two of said memory module slots; a plurality of said memory module slots including means for receiving at least two different types of memory modules having differing amounts of memory storage; the steps of the method comprising: assigning a predefined address range to each memory module slot solely on the basis of a type of memory module, if any, inserted therein, each assigned predefined address range being independent of which type of memory module, if any, are inserted in other ones of said memory module slots; receiving sets of address signals transmitted on said address bus; and decoding each said set of address signals, and generating a memory module enable signal corresponding to one of said memory module slot means whenever said set of address signals define an address in one of said predefined address ranges assigned to said plurality of memory module slots; wherein each said memory module slot has a fixed, predefined address range assigned thereto for each different type of memory module which it has means for receiving, and said assigned address ranges for memory module slots with memory modules inserted therein need not be contiguous; whereby memory modules can be inserted in any selected ones of said memory module slots without regard to corresponding address ranges assigned thereto.
Claim 8
Independent Claim
270 words
A method of accessing data storage locations in a computer memory system, said computer memory system including an address bus for transmitting sets of address signals, each set of address signals defining an address in a predefined address space, and a plurality of memory module slots, coupled to said address bus, with memory modules inserted in at least two of said memory module slots; a plurality of said memory module slots including means for receiving at least two different types of memory modules having differing amounts of memory storage; the steps of the method comprising: assigning a predefined address range to each memory module slot solely on the basis of a type of memory module, if any, inserted therein, each assigned predefined address range being independent of which type of memory module, if any, are inserted in other ones of said memory module slots; receiving sets of address signals transmitted on said address bus; and decoding each said set of address signals, and generating a memory module enable signal corresponding to one of said memory module slot means whenever said set of address signals define an address in one of said predefined address ranges assigned to said plurality of memory module slots; wherein each said memory module slot has a fixed, predefined address range assigned thereto for each different type of memory module which it has means for receiving, and said assigned address ranges for memory module slots with memory modules inserted therein need not be contiguous; whereby memory modules can be inserted in any selected ones of said memory module slots without regard to corresponding address ranges assigned thereto.
Claim 9
Dependent Claim
86 words
The method of accessing data storage locations in a computer memory system set forth in claim 6, including: generating a module type signal denoting the type of each said memory module and an amount of memory storage in said memory module; and receiving said module type signal for each said memory module, determining the predefined address range corresponding to said received module type signal for each said memory module, and enabling access only to memory locations within said predefined address ranges corresponding to said memory modules.
Claim 10
Dependent Claim
115 words
The method of accessing data storage locations in a computer memory system set forth in claim 6, including: generating a module type signal denoting the type of each said memory module and an amount of memory storage in said memory module; receiving said module type signals for each said memory module and determining the predefined address range corresponding to said received module type signal for each said memory module; and denoting lists of pages of predetermined size within each of said predefined address ranges corresponding to said memory modules, and enabling access only to memory locations within said pages denoted in said lists; whereby access to memory locations not occupied by memory modules is prevented.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |