Memory board automatically assigned its address range by its position

Claim 2

A memory board in which a plurality of memory locations are arranged thereon by mounting a plurality of memory chips, comprising: (A) first terminals for receiving address information for specifying one of said memory locations; (B) second terminals for receiving start address information corresponding to the first memory location of those memory locations; (C) means for supplying memory capacity information representing a capacity of the plurality of memory locations; (D) addition means for adding the start address information to the memory capacity information; (E) third terminals through which the output information of said addition means is outputted; (F) subtraction means for subtracting the start address information from the address information; and (G) means for producing a selection signal for selecting a memory board when the information (the address information--the start address information) outputted from the subtraction means is given by the following expression: 0≦(the address information--the start address information)<the memory capacity information.

Claim 3

A memory board according to claim 1, wherein said means for supplying the memory capacity information is supplied by wiring a jumper line to represent the memory capacity when said memory board is manufactured.

Claim 4

A memory board according to claim 1, wherein the information outputted from said third terminals of a memory board when the plurality of memory boards are inserted into a mother board, is supplied to said second terminals of the next memory board through the wiring on the mother board.

Claim 5

A memory board according to claim 1, wherein said start address information is taken as the address 0 within the memory board by means of said subtractor means.

Claim 6

A memory board according to claim 1, wherein the information outputted from said subtractor means is used as the address to specify one of the memory locations within the memory board.

Claim 7

A memory board according to claim 1, wherein said means for producing the selection signal includes a comparing circuit for comparing the output information from said subtractor means with the memory capacity information, and a gate circuit into which a signal as an inversion of a borrow signal outputted from said subtractor circuit and an output signal from said comparing circuit are applied.

Claim 8

A memory board in which a plurality of memory locations 2 m K to 2 n K (m and n are integers, m<n, and K=1,024) are supplied by mounting a discretionary number of memory chips on the memory board, comprising: (A) first terminals for receiving address information for specifying memory locations of 2 n+a K (a is an integer of 1 or more); (B) second terminals for receiving start address information of a train of bits (n+a-m) for the start address location of the plurality of memory locations; (C) means for jumper-wiring one of the terminals of (n+a-m) to produce memory capacity information of (n+a-m) bits representing the plurality of the memory locations; (D) addition means for adding the start address information of a train of the (n+a-m) bits to the memory capacity information of a train of the (n+a-m) bits; (E) third terminals through which the output information of said addition means is outputted; (F) means for subtracting the start address information of a train of the (n+a-m) bits from the address information ranging from 2 m K bits to 2 n+a K bits of those pieces of information; (G) means for producing a selection signal for selecting a memory board when the output information from said subtraction means is given by the following expression: 0≦(address information ranging from 2 m K bits to 2 n+a K bits--start address information of a train of (n+a-m) bits<memory capacity information of a train of (n+a-m) bits; (H) means for taking as the address for specifying the plurality of memory locations the information which the sum of the upper bits of the address information of 2 m-1 K bits or less of the information supplied from said first terminals and the output information of said subtraction means.

Claim 9

A memory board in which a plurality of memory locations 2 m K to 2 n K (m and n are integers, m<n, and K=1,024) are supplied by mounting a discretionary number of memory chips on the memory board, comprising: (A) first terminals for receiving address information for specifying memory locations of 2 n+a K (a is an integer of 1 or more); (B) second terminals for receiving start address information of a train of bits (n+a-m) for the start address location of the plurality of memory locations; (C) means for jumper-wiring one of the terminals of (n+a-m) to produce memory capacity information of (n+a-m) bits representing the plurality of the memory locations; (D) addition means for adding the start address information of a train of the (n+a-m) bits to the memory capacity information of a train of the (n+a-m) bits; (E) third terminals through which the output information of said addition means is outputted; (F) means for subtracting the start address information of a train of the (n+a-m) bits from the address information ranging from 2 m K bits to 2 n+a K bits of those pieces of information; (G) means for producing a selection signal for selecting a memory board when the output information from said subtraction means is given by the following expression: 0≦(address information ranging from 2 m K bits to 2 n+a K bits--start address information of a train of (n+a-m) bits<memory capacity information of a train of (n+a-m) bits; (H) means for taking as the address for specifying the plurality of memory locations the information which the sum of the upper bits of the address information of 2 m-1 K bits or less of the information supplied from said first terminals and the output information of said subtraction means.

Claim 10

A memory board according to claim 1 or 7, wherein, when a plurality of the memory boards are inserted into a mother board, an address range of each memory board is automatically set by the output information of said addition means of the preceding memory board and the memory capacity information previously prepared on said each memory board.

Claim 11

A memory board in which a plurality of memory locations 2 m K to 2 n K (m and n are integers, m<n, and K=1,024) are supplid by mounting a discretionary number of memory chips on the memory board; (A) first terminals for receiving address information for specifying memory locations of 2 m+1 K; (B) second terminals for receiving start address information of a train of (n+1-m) bits for the first address location of the plurality of memory locations; (C) means for jumper-wiring one of the terminals of (n+1-m) to produce memory capacity information (n+1-m) bits representing the plurality of memory locations; (D) third terminals through which an inversion of the start address information of the (n+1-m) bits is outputted; (E) exclusive OR circuits of (n+1-m) bits into which the address information of (2 m K bits to 2 n+1 K bits) and the start address information of (n+1-m) are correspondingly applied; (F) logical gate means for producing a board selection signal when the most significant bit of logical "1" signals produced from said exclusive OR circuits of (n+1-m) is smaller than the most significant bit to address the memory capacity given by the terminal jumper-wired, or when the output signals from said exclusive OR circuits of (n+1-m) are all logical "0"; and (G) means for specifying the plurality of memory locations for using the address information necessary for addressing the memory capacity given by the terminal jumper-wired of those pieces of address information.

Claim 12

A memory board in which a plurality of memory locations 2 m K to 2 n K (m and n are integers, m<n, and K=1,024) are supplid by mounting a discretionary number of memory chips on the memory board; (A) first terminals for receiving address information for specifying memory locations of 2 m+1 K; (B) second terminals for receiving start address information of a train of (n+1-m) bits for the first address location of the plurality of memory locations; (C) means for jumper-wiring one of the terminals of (n+1-m) to produce memory capacity information (n+1-m) bits representing the plurality of memory locations; (D) third terminals through which an inversion of the start address information of the (n+1-m) bits is outputted; (E) exclusive OR circuits of (n+1-m) bits into which the address information of (2 m K bits to 2 n+1 K bits) and the start address information of (n+1-m) are correspondingly applied; (F) logical gate means for producing a board selection signal when the most significant bit of logical "1" signals produced from said exclusive OR circuits of (n+1-m) is smaller than the most significant bit to address the memory capacity given by the terminal jumper-wired, or when the output signals from said exclusive OR circuits of (n+1-m) are all logical "0"; and (G) means for specifying the plurality of memory locations for using the address information necessary for addressing the memory capacity given by the terminal jumper-wired of those pieces of address information.

Claim 13

A memory board in which a plurality of memory locations 2 m K to 2 n K (m and n are integers, m<n, and K=1,024) are supplied by mounting a discretionary number of memory chips on the memory board, (A) first terminals for receiving address information for specifying memory locations 2 n+1 K; (B) second terminals for receiving information of (n+1-m) bits; (C) third terminals for receiving logical information of logical "0" or "1"; (D) first logic gate means for receiving the logical information coming from said third terminals and information of (n+1-m) bits coming from said second terminals and for responding to both the information to supply the start address to the first memory location of the plurality of the memory locations; (E) means for jumper-wiring one of the terminals of (n+1-m) to produce memory capacity information of (n+1-m) bits representing the plurality of the memory locations; (F) second logic gate means for receiving the memory capacity information of (n+1-m) bits and the information as an inversion of the logical information coming from said third terminals, and for producing the information to the corresponding second terminals; (G) exclusive OR circuits (n+1-m) for receiving the address information of (2 m K bits to 2 n+1 K bits) and the start address information of (n+1-m) bits; (H) third logic gate means for producing a board selection signal when the most significant bit of logical "1" signals produced from said exclusive OR circuit of (n+1-m) is smaller than the most significant bit to address the memory capacity given by the terminal jumper-wired, or when the output signals from said exclusive OR circuits of (n+1-m) are all logical "0"; and (I) means for specifying the plurality of memory locations for using the address information necessary for addressing the memory capacity given by the terminal jumper-wired of those pieces of information.

Claim 14

A memory board in which a plurality of memory locations 2 m K to 2 n K (m and n are integers, m<n, and K=1,024) are supplied by mounting a discretionary number of memory chips on the memory board, (A) first terminals for receiving address information for specifying memory locations 2 n+1 K; (B) second terminals for receiving information of (n+1-m) bits; (C) third terminals for receiving logical information of logical "0" or "1"; (D) first logic gate means for receiving the logical information coming from said third terminals and information of (n+1-m) bits coming from said second terminals and for responding to both the information to supply the start address to the first memory location of the plurality of the memory locations; (E) means for jumper-wiring one of the terminals of (n+1-m) to produce memory capacity information of (n+1-m) bits representing the plurality of the memory locations; (F) second logic gate means for receiving the memory capacity information of (n+1-m) bits and the information as an inversion of the logical information coming from said third terminals, and for producing the information to the corresponding second terminals; (G) exclusive OR circuits (n+1-m) for receiving the address information of (2 m K bits to 2 n+1 K bits) and the start address information of (n+1-m) bits; (H) third logic gate means for producing a board selection signal when the most significant bit of logical "1" signals produced from said exclusive OR circuit of (n+1-m) is smaller than the most significant bit to address the memory capacity given by the terminal jumper-wired, or when the output signals from said exclusive OR circuits of (n+1-m) are all logical "0"; and (I) means for specifying the plurality of memory locations for using the address information necessary for addressing the memory capacity given by the terminal jumper-wired of those pieces of information.

Claim 15

A memory board according to claims 9 and 10, wherein when a first memory board is inserted into a slot 0 of a mother board and a second memory board is inserted into a slot 1 of the mother board, the memory capacity of said first memory board is equal to that of said second memory board or the memory capacity of said second memory board is larger than that of said second memory board.

Claim 16

A memory board according to claim 10, wherein, when a first memory board is inserted into a slot 0 of a mother board and a second memory board is inserted into a slot 1 of the mother board, a logical "0" signal is supplied through said third terminals of said first memory board and a logical "1" signal is supplied to said third terminals of said second memory board.