Self-adaptive computer memory address allocation system

Claim 1

A computer memory address allocation system for connection to first and second memory modules each comprised of a plurality of memory banks, predetermined ones of said memory banks having one or more memory circuits connected thereto, comprising: (a) a main controller for successively storing and retrieving data signals to and from respective ones of said memory banks, comparing said stored and retrieved data signals, and in response generating first and second control signals indicative of the number of said memory banks in each of said first and second modules which have memory circuits connected thereto; (b) first and second programmable logic circuits connected to said main controller and said first and second memory modules, for receiving said first and second control signals, respectively, and further ones of said address signals, and in response generating enable signals for enabling said predetermined memory banks having memory circuits connected thereto are addressed and enabled as contiguous memory; (c) refresh control circuitry for periodically generating refreshed signals; and (d) first and second row and column address decoding circuits connected to said refresh control circuitry, and to said first and second programmable logic circuits respectively, for generating row and column select signals for enabling rows and columns of said memory banks in response to receiving one or more of said refresh signals or said enable signals; wherein each of said row and column address decoding circuits includes an inverter connected to said main controller, for receiving a memory select control signal therefrom, a delay circuit connected to said inverter, for delaying said received memory select control signal, a first plurality of NAND gates having inputs connected to said refresh control circuitry and predetermined outputs of a corresponding one of said programmable logic circuits, a plurality of NOT gates having inputs connected to said outputs of the corresponding one of the programmable logic circuits, for receiving and inverting said enable signals, a second plurality of NAND gates having first inputs connected to outputs of said plurality of NAND gates and second inputs connected to said inverter, for generating said row select signals in response to receiving said memory select control signal and generation of one of said refresh or enable signals, and a third plurality of NAND gates first inputs connected to said NOT gates and second inputs connected to said delay circuits, for generating said column select signals in response to receiving a delayed version of said memory signal and said inverted enable signals.