Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
210 words
In a programmable controller for selectively connecting and disconnecting a power signal to each of a plurality of output devices in response to computed respective on/off states generated by execution of a stored control program on a plurality of binary parameters, wherein the value of each of said parameters corresponds to a state of a respective input device, a variable module memory for storing said control program comprising: a. a set of up-to-N memory modules, each for storing a plurality of program instructions of n binary bits each; b. N receptacle means for receiving said set of up-to-N memory modules, and for coupling each of the received memory modules to a common serial output bus; c. memory address control means coupled via said receptacle means to said up-to-N memory modules for providing address signals for sequentially addressing each of ten memory modules and sequentially addressing the program instruction words of the addressed memory module to provide the contents stored therein in series to said common serial output bus; and d. means for detecting the absence of memory modules in said receptables and for forcing said common serial data output bus to a predetermined binary state for all bits of all program instruction words of vacant ones of said receptable means.
Claim 2
Dependent Claim
210 words
In a programmable controller for selectively connecting and disconnecting a power signal to each of a plurality of output devices in response to computed respective on/off states generated by execution of a stored control program on a plurality of binary parameters, wherein the value of each of said parameters corresponds to a state of a respective input device, a variable module memory for storing said control program comprising: a. a set of up-to-N memory modules, each for storing a plurality of program instructions of n binary bits each; b. N receptacle means for receiving said set of up-to-N memory modules, and for coupling each of the received memory modules to a common serial output bus; c. memory address control means coupled via said receptacle means to said up-to-N memory modules for providing address signals for sequentially addressing each of ten memory modules and sequentially addressing the program instruction words of the addressed memory module to provide the contents stored therein in series to said common serial output bus; and d. means for detecting the absence of memory modules in said receptables and for forcing said common serial data output bus to a predetermined binary state for all bits of all program instruction words of vacant ones of said receptable means.
Claim 3
Dependent Claim
69 words
In the programmable controller according to claim 1, said means for detecting the absence of a memory module in a receptacle means and for forcing said common serial data output bus to a predetermined binary state comprising a pull-up resistor connecting said common serial output bus to a predetermined voltage source to force said output bus to said predetermined binary state when no data is read from said memory.
Claim 4
Dependent Claim
33 words
In the programmable controller according to claim 1, said controller being responsive to a program instructor wherein all bits of said program instruction are of said predetermined binary state as a NO-OP instruction.
Claim 5
Dependent Claim
30 words
In the programmable controller according to claim 1, each of said memory modules being an integrated circuit and said receptable being an integrated circuit socket for receiving said integrated circuit.
Claim 6
Dependent Claim
130 words
A variable module memory comprising: a. a set of up-to-N memory modules, each for storing a plurality of words of n bits; b. N receptable means for receiving said set of up-to-N memory modules, and for coupling each of the received memory modules to a common serial output bus; c. memory address control means coupled via said receptable means to said up-to-N memory modules for providing address signals for selectively addressing words of selected ones of said memory module to provide the contents stored therein in series to said common serial output bus; and d. means for detecting the absence of memory modules in said receptacles and for forcing said common serial output bus to a predetermined binary state for all bits of all addressed words of vacant receptacle means.
Claim 7
Dependent Claim
130 words
A variable module memory comprising: a. a set of up-to-N memory modules, each for storing a plurality of words of n bits; b. N receptable means for receiving said set of up-to-N memory modules, and for coupling each of the received memory modules to a common serial output bus; c. memory address control means coupled via said receptable means to said up-to-N memory modules for providing address signals for selectively addressing words of selected ones of said memory module to provide the contents stored therein in series to said common serial output bus; and d. means for detecting the absence of memory modules in said receptacles and for forcing said common serial output bus to a predetermined binary state for all bits of all addressed words of vacant receptacle means.
Claim 8
Dependent Claim
52 words
The memory system according to claim 5, wherein said means for detecting the absence of a memory module in a receptacle means and for forcing said common serial data output bus to said predetermined binary state comprises a pull-up resistor for coupling said common serial data output bus to a predetermined voltage.