Memory presence checking apparatus

Claim 2

For use in a data processing system including: an addressable memory system including a plurality of memory planes, each plane having a plurality of storage locations, address register means for storing address signals designating a planE and a storage location within said plane to be accessed, decoding circuit means coupled to said address register means and individually to each of said planes, said decoding means being operative in response to a command signal from said processing system to initiate a memory cycle of operation by applying said command signal to a designated one of said planes for accessing information stored in one of said plurality of storage locations designated by said address signals, register means coupled to said memory system, said register means for storing said information of a referenced storage location, checking apparatus comprising: a plurality of logic circuit means, one individually coupled to be associated with each of said plurality of planes, each one being connected to receive a predetermined signal from said associated plane indicating whether said plane is included in said memory system and each one of said logic circuit means being operative to generate an output signal upon the application of said command signal only when conditioned by said predetermined signal during said memory cycle of operation; and, output means being operatively coupled to each of said plurality of logic circuit means and to an output terminal, said output means being operative in response to said output signal from a logic circuit means of a selected plane to return a control signal to said output terminal indicating to said processing system that the storage location accessed during the memory cycle of operation is physically present.

Claim 3

In the system according to claim 1 wherein said system further includes: parity checking means coupled to said register means, said parity check means being operative to perform an odd parity check based upon the contents of said register means and said parity checking means including means for generating an error signal upon the occurrence of a parity error condition; and, control store means coupled to said means, said control store means being operative to generate subcommand signals for directing the system during a cycle of operation and said control store means being conditioned by said error signal to generate subcommand signals for testing said output means to determine whether said parity error condition was caused by referencing during a previous memory cycle of operation a storage location which is not present.

Claim 4

In the system of claim 2 wherein said output means includes: bistable switching means, said bistable switching means being operative in response to said control signal to switch from a first state to a second state and said bistable switching means being coupled to said control store means, said bistable switching means being conditioned by said signals from said control store means to be switched from said second to said first state at the completion of a memory cycle of operation.

Claim 5

In the system according to claim 1 wherein said checking apparatus further includes: a plurality of circuit means, one circuit means being individually associated with each of said plurality of logic circuit means, and each of said plurality of memory planes, each one of circuit means including connector means being connected to a predetermined reference potential when the associated plane is electrically connected to said memory system producing said predetermined signal.

Claim 6

In the system according to claim 4 wherein said plurality of logic circuit means each include: first gating means having first and second input terminals and an output terminal, said first input terminal being connected to receive said control signal from said decoding means; and, second gating means having an input terminal and an output terminal, said input terminal being connected to receive said predetermined signal from an associated one of said circuit means and said output terminal being connected in common with said output terminal of said first gating means; and wherein said checking apparatus includes: first conductor means for coupling said output terminals of said first and second gating means of the one of said logic circuit means associated with a plane designated by the lowest address to said output means; and second conductor means for coupling the output terminals of said first and second gating means of each one of the remaining logic circuit means to the second input terminal of said first gating means of said logic circuit means associated with a plane designated by the next lowest address, any one of said first gating means being operative in response to said control signal to inhibit a transfer of signals to said output means from any one of the logic circuit means associated with planes designated by addresses higher than the plane designed for access and said first and second gating means of each of the logic circuit means associated with planes designated by addresses lower than said plane designated for access being conditioned by the predetermined signal of an associated plane to apply a signal to said output means only when all of the planes designated by said lower addresses have been signalled by associated circuit means as being connected.

Claim 7

The system of claim 5 wherein each of said first gating means of said logic circuit means includes an AND gate.

Claim 8

In the system according to claim 4 wherein said plurality of logic circuit means each include: gating means having first and second input terminals and an output terminal, said first input terminal being connected to receive said control signal from said decoding means; and wherein said checking apparatus further includes: first conductor means for coupling said output terminal of said gating means of the one of said logic circuit means associated with a plane designated by the lowest address to said output terminal; and second conductor means for coupling the output terminals of said gating means of each one of the remaining logic circuit terminals of the gating means of said logic circuit means associated with a plane designated by the next lowest address, any one of said gating means in response to said control signal being operative to inhibit a transfer of signals to said output means from any one of the logic means associated with planes designated by addresses higher than the plane designated for access and said gating means of the logic circuit means associated with planes designated by addresses lower than said plane designated for access being operative to apply a signal to said output means in response to said control signal only when all of the planes designated by said lower addresses are connected in said memory system.

Claim 9

In the system of according to claim 7 wherein said gating means of each of said plurality of logic circuit means includes an AND gate.

Claim 10

In the system according to claim 4 wherein said plurality of logic circuits each include: gating means having an input terminal and an output terminal, said input terminal being connected to receive said control signal from said decoding means and wherein said checking means further includes conductor means connected to the output terminal of each of said gating means in common to said output means, each of said gating means being operative in response to said control signal to apply a signal to said output means only when the associated plane is connected in said memory system.

Claim 11

A terminal system comprising: addressable main memory means having a plurality of memory sections, each section having a plurality of storage locations; address register means coupled to said main memory means, said register means for storing signals identifying a section and storage location within said section to be referenced during a memory cycle of operation, and said address register means including means for modifying said signals to reference a next sequential storage location in said memory means; decoding means coupled to said address register means and to each of said mEmory sections, said decoding means being operative in response to a command control signal from said terminal system to apply said control signal to a designated one of said memory sections for initiating the read out of the contents of a designated storage location during a memory cycle of operation; register means coupled to said main memory means, said register means for storing the contents of a referenced location; control signal generating means, said control means being operative to generate subcommand signals for directing said system during a cycle of operation; and, memory checking apparatus comprising: a plurality of circuit means, one circuit means individually associated with each of said plurality of memory sections, each one being connected to generate a control signal when said associated section is physically connected in said memory means; a plurality of logic circuit means, one individually associated with each of said plurality of circuit means for receiving a control signal from said one circuit means and each of said plurality of logic circuit means being coupled to said decoding means, said each one logic circuit means being operative in response to said command control signal to generate an output signal only when conditioned by the control signal from said associated circuit means; and, output means coupled to said control means and to each of said plurality of logic circuit means for receiving said output signal; said control means being operative in response to a first input control signal to generate a sequence of subcommand signals which initiate a series of memory cycles of operation, said address register means being forced to a predetermined state for referencing a first storage location in said memory means, said output means being operative in response to the occurrence of said control signal during each memory cycle to enable said control means condition said address register means to reference a next sequential storage location and said output means being operative upon referencing a first storage location which fails to produce said control signal to condition said control means to force said address register means to another predetermined state for referencing a predetermined storage location in said memory means for storing a signal representation of the address of said first storage location corresponding to the maximum amount of contiguous memory available within said memory means.

Claim 12

A terminal system comprising: addressable main memory means having a plurality of memory sections, each section having a plurality of storage locations; address register means coupled to said main memory means, said register means for storing signals identifying a section and storage location within said section to be referenced during a memory cycle of operation, and said address register means including means for modifying said signals to reference a next sequential storage location in said memory means; decoding means coupled to said address register means and to each of said mEmory sections, said decoding means being operative in response to a command control signal from said terminal system to apply said control signal to a designated one of said memory sections for initiating the read out of the contents of a designated storage location during a memory cycle of operation; register means coupled to said main memory means, said register means for storing the contents of a referenced location; control signal generating means, said control means being operative to generate subcommand signals for directing said system during a cycle of operation; and, memory checking apparatus comprising: a plurality of circuit means, one circuit means individually associated with each of said plurality of memory sections, each one being connected to generate a control signal when said associated section is physically connected in said memory means; a plurality of logic circuit means, one individually associated with each of said plurality of circuit means for receiving a control signal from said one circuit means and each of said plurality of logic circuit means being coupled to said decoding means, said each one logic circuit means being operative in response to said command control signal to generate an output signal only when conditioned by the control signal from said associated circuit means; and, output means coupled to said control means and to each of said plurality of logic circuit means for receiving said output signal; said control means being operative in response to a first input control signal to generate a sequence of subcommand signals which initiate a series of memory cycles of operation, said address register means being forced to a predetermined state for referencing a first storage location in said memory means, said output means being operative in response to the occurrence of said control signal during each memory cycle to enable said control means condition said address register means to reference a next sequential storage location and said output means being operative upon referencing a first storage location which fails to produce said control signal to condition said control means to force said address register means to another predetermined state for referencing a predetermined storage location in said memory means for storing a signal representation of the address of said first storage location corresponding to the maximum amount of contiguous memory available within said memory means.

Claim 13

The system of claim 10 wherein said control means includes means for receiving a second input control signal, said control means being conditioned by said second input control signal to generate subcommand signals for initiating another memory cycle of operation, said address register means being forced to said another predetermined state for referencing said predetermined storage location for read out of said signal representations corresponding to said maximum address into said register means.

Claim 14

The system of claim 10 wherein said plurality of circuit means, each includes connector means coupled to said associated memory section, each connector means being connected to a predetermined reference potential when said associated memory section is electrically connected into said memory means.

Claim 15

The system of claim 12 wherein each said connector means includes a pin connector and said predetermined reference potential corresponds to a ground potential.

Claim 16

The system of claim 10 wherein said plurality of logic circuit means each include: first gating means having first and second terminals and an output terminal, said first input terminal being connected to receive said control signal from said decoding means; and, second gating means having an input terminal and an output terminal, said input terminal being connected to receive said predetermined signal from an associated one of said circuit means and said output terminal being connected in common with said output terminal of said first gating Means; and wherein said checking apparatus further includes: first conductor means for coupling said output terminals of said first and second gating means of the one of said logic circuit means associated with a plane designated by the lowest address to said output means; and second conductor means for coupling the output terminals of said first and second gating means of each one of the remaining logic circuit means to the second input terminal of said first gating means of said logic circuit means associated with a plane designated by the next lowest address, any one of said first gating means being operative in response to said control signal to inhibit a transfer of signals to said output means from any one of the logic circuit means associated with planes designated by addresses higher than the plane designed for access and said first and second gating means of each of the logic circuit means associated with planes designated by addresses lower than said plane designated for access being conditioned by the predetermined signal of an associated plane to apply a signal to said output means only when all of the planes designated by said lower addresses have been signalled by associated circuit means as being connected.

Claim 17

The system of claim 14 wherein each of said first gating means of said logic circuit means includes an AND gate.

Claim 18

The system of claim 10 wherein said plurality of logic circuit means each include: gating means having first and second input terminals and an output terminal, said first input terminal being connected to receive said control signal from said decoding means; and wherein said checking apparatus further includes: first conductor means for coupling said output terminal of said gating means of the one of said logic circuit means associated with a plane designated by the lowest address to said output terminal; and second conductor means for coupling the output terminals of said gating means of each one of the remaining logic circuit terminal of the gating means of said logic circuit means associated with a plane designated by the next lowest address, any one of said gating means in response to said control signal being operative to inhibit a transfer of signals to said output means from any one of the logic means associated with planes designated by addresses higher than the plane designated for access and said gating means of the logic circuit means associated with planes designated by addresses lower than said plane designated for access being operative to apply a signal to said output means in response to said control signal only when all of the planes designated by said lower addresses are connected in said memory system.

Claim 19

The system of claim 16 wherein said gating means of each of said plurality of logic circuit means includes an AND gate.

Claim 20

The system of claim 10 wherein said plurality of logic circuits each include: gating means having an input terminal and an output terminal, said input terminal being connected to receive said control signal from said decoding means and wherein said checking means further includes conductor means connected to the output terminal of each of said gating means in common to said output means, each of said gating means being operative in response to said control signal to apply a signal to said output means only when the associated plane is connected in said memory system.

Claim 21

The system of claim 10 wherein said system further includes: data transfer means coupled to said register means, said transfer means being conditioned by said control means to transfer said signal representation to a remote source.

Claim 22

In a data processing system including: an addressable memory means including a plurality of installable memory sections, said plurality of sections being arranged to form a contiguous addressable memory space when installed in said memory means, each section having a plurality of storage locations and means coupled to apPly select signals during a memory cycle of operation to an addressed one of said plurality of sections for accessing information stored in one of said plurality of storage locations; register means coupled to said memory means for storing the information of a referenced storage location, said system further including checking apparatus comprising: a plurality of circuit means, one individually associated with each of said plurality of sections, each one of said circuit means being operative to generate a predetermined signal level when the associated section is connected in said memory means; a plurality of logic circuit means, one individually associated with each of said plurality of circuit means for receiving a predetermined signal level from a corresponding one of said logic circuit means, each of said logic circuit means being coupled to said means for receiving a predetermined one of said signals designating when the associated section has been selected for access; and, output means being operatively coupled to each of said plurality of logic circuit means, each of said logic circuit means being operative in response to said select signals when conditioned by said predetermined signal level to condition said output means to generate a return control signal for indicating to said system that the storage location accessed during the memory cycle of operation is installed.

Claim 23

In a data processing system including: an addressable memory means including a plurality of installable memory sections, said plurality of sections being arranged to form a contiguous addressable memory space when installed in said memory means, each section having a plurality of storage locations and means coupled to apPly select signals during a memory cycle of operation to an addressed one of said plurality of sections for accessing information stored in one of said plurality of storage locations; register means coupled to said memory means for storing the information of a referenced storage location, said system further including checking apparatus comprising: a plurality of circuit means, one individually associated with each of said plurality of sections, each one of said circuit means being operative to generate a predetermined signal level when the associated section is connected in said memory means; a plurality of logic circuit means, one individually associated with each of said plurality of circuit means for receiving a predetermined signal level from a corresponding one of said logic circuit means, each of said logic circuit means being coupled to said means for receiving a predetermined one of said signals designating when the associated section has been selected for access; and, output means being operatively coupled to each of said plurality of logic circuit means, each of said logic circuit means being operative in response to said select signals when conditioned by said predetermined signal level to condition said output means to generate a return control signal for indicating to said system that the storage location accessed during the memory cycle of operation is installed.

Claim 24

The system of claim 20 wherein said system further includes: parity checking means coupled to said register means, said parity check means being operative to perform a parity check operation upon the contents of said register means and said parity check means including means for generating an error signal upon the occurrence of a parity error condition; cycled addressable control store means, said control store means including a plurality of storage locations for storing microinstruction words of a plurality of microprogram routines; decoding means coupled to said control store means for generating a plurality of subcommand signals in response to each microinstruction word referenced during a cycle of operation; bistable storage means coupled to said output means and to said decoding means, said bistable means being operative in response to said return control signal to switch from a first state to a second state, said control store means being conditioned by said error signal to reference a predetermined one of said plurality of microprogram routines and said decoding means being operative in response to the microinstruction words of said routine to generate subcommand signals for testing the state of said bistable storage means and for generating a signal indicating that said error was caused by addressing an uninstalled storage location when said bistable means has not been switched to said second state.

Claim 25

The system of claim 20 wherein said system further includes: address register means coupled to said means of said memory means, said address register means for storing signals identifying a section and storage location within said section to be accessed during a memory cycle of operation; cycled addressable control store means, said control store means including a plurality of storage locations for storing microinstruction words of a plurality of microprogram routines; decoding means coupled to said control store means for generating a plurality of subcommand signals in response to each microinstruction word referenced during a cycle of operation; and, bistable storage means coupled to said output means and to said decoding means, said bistable means being operative in response to said return control signal to switch from a first state to a second state and said bistable means being conditioned by a predetermined one of said plurality of subcommand signals to be switched from said second state to said first state; said control store means being operative in response to a first control signal to reference a predetermined One of said plurality of microprogram routines and said decoding means being operative in response to the microinstruction words of said routine to generate subcommand signals for conditioning said address register means for addressing in sequence storage locations of said memory means starting from an initial address during successive memory cycles of operation, and switching said bistable means from said second to said first state, said control store means being conditioned by the state of said bistable means upon addressing a storage location which did not switch said bistable means to said second state to cause said address register means to reference a predetermined storage location in said memory means for storing a signal representation of the address of said storage location to identify the maximum amount of continguous memory storage locations within said memory means.

Claim 26

The system of claim 22 wherein said control store means includes means for receiving a second control signal, said control store means being conditioned by said second signal to reference another predetermined one of said plurality of microprogram routines, said decoding means being operative in response to the microinstruction words of said routine to generate subcommand signals for conditioning said address register means to reference said predetermined storage location for read out of said signal representations corresponding to a maximum address to said register means.

Claim 27

The system of claim 22 wherein said predetermined one of said microprogram routines is included as part of an initialization microprogram routine stored in said control store means, and wherein said control store means includes means for receiving an initialization control signal, said control store means being conditioned by said control signal to reference said routine and said decoding means being operative in response to the microinstruction words of said routine to generate subcommand signals for testing the operation of said memory means before referencing said predetermined one of said routines.

Claim 28

The system of claim 20 wherein said means of said memory means includes: a plurality of gating means, one individually associated with a pair of said plurality of logic circuit means, each of said plurality of gating means including: first gating means for receiving a read command signal; second gating means coupled to said first gating means and connected to receive a plurality of address signals coded to designate either one of pair of said plurality of memory sections; and first and second output gating means, each being coupled to said second gating means and connected to receive another address signal; one of said first and second output gating means of each of said plurality of gating means being operative in response to said read command signal to apply a selection signal to the associated one of the pair of said plurality of logic circuit means only when all of said address signals are coded to select the section associated with said logic circuit means.

Claim 29

The system of claim 25 wherein each of said first and second output gating means of each of said plurality of gating means includes a NAND gate.

Claim 30

The system of claim 26 wherein said plurality of logic circuit means, each include: first gating means having first and second input terminals and an output terminal, said first input terminal being connected to receive said control signal from said decoding means; and, second gating means having an input terminal and an output terminal, said input terminal being connected to receive said predetermined signal from an associated one of said circuit means and said output terminal being connected in common with said output terminal of said first gating means; and, wherein said checking apparatus further includes: first conductor means for coupling said output terminals of said first and second gating means of the one of said logic circuit means associated wIth a plane designated by the lowest address to said output means; and second conductor means for coupling the output terminals of said first and second gating means of each one of the remaining logic circuit means to the second input terminal of said first gating means of said logic circuit means associated with a plane designated by the next lowest address, any one of said first gating means being operative in response to said control signal to inhibit a transfer of signals to said output means from any one of the logic circuit means associated with planes designated by addresses higher than the plane designed for access and said first and second gating means of each of the logic circuit means associated with planes designated by addresses lower than said plane designated for access being conditioned by the predetermined signal of an associated plane to apply a signal to said output means only when all of the planes designated by said lower addresses have been signalled by associated circuit means as being connected.