Interrupt reporting for single-bit memory errors

Claim 2

Apparatus for use in a computer system which operates to provide error information including an indication that a memory error has occurred and, at least for some memory errors, an identifier of the portion of memory where the error occurred, comprising: register means for storing at least a portion of the error information for the most recent previous error; comparison means, responsive to the stored error information and to incoming error information, for providing an indication whether they differ; means, responsive to the occurrence of an error, for transferring the corresponding portion of the incoming error information into said register means; and means for generating an interrupt signal, operable in at least one mode to generate an interrupt signal only if said comparison means indicates a difference and at least one type of error has occurred.

Claim 3

The apparatus of claim 1 wherein said means for generating an interrupt signal is effective only for single-bit errors.

Claim 4

The apparatus of claim 1 wherein said means for transferring is effective for single-bit errors and at least one other type of error.

Claim 5

The apparatus of claim 1 wherein: the memory comprises memory chips and is organized in banks that are one chip high by N chips wide where N is the number of bits in a word; the error information includes a first error signal specifying that a single-bit error has occurred, a second error signal specifying that some error has occurred, a bank number field, and a syndrome field where at least some values of the syndrome specify that a single-bit error occurred and identify the chip number in the bank where the single-bit error occurred.

Claim 6

The apparatus of claim 1 wherein said means for generating an interrupt is operable in at least one additional mode to generate an interrupt signal whenever said at least one type of error has occurred, regardless of the indication from said comparison means.

Claim 7

The apparatus of claim 1 wherein said means for comparing comprises a plurality of exclusive OR gates.

Claim 8

The apparatus of claim 1 wherein: said means for generating an interrupt signal is effective only for single-bit errors; said means for transferring is effective for single-bit errors and at least one other type of error; and said means for generating an interrupt is operable in at least one additional mode to generate an interrupt signal whenever a single-bit error has occurred, regardless of the indication from said comparison means.

Claim 9

Apparatus for use in a computer system which operates to provide error information, including a first error signal specifying that a single-bit error has occurred, a second error signal specifying that some error has occurred, a bank number field that specifies a region in memory where an error has occurred, a syndrome field where at least some values of the syndrome specify that a single-bit error has occurred in a particular sub-region of memory, comprising: register means having a data input and a clock input for storing a bank and syndrome provided at the time of the most recent previous error; means for applying the incoming bank and syndrome to said data input of said register means; comparison means for providing an indication whether the stored bank and syndrome differ from the incoming bank and syndrome; means, responsive to the second error signal, for providing a clock signal at said clock input of said register means for transferring the incoming bank and syndrome into said register means; and means for generating an interrupt signal, operable in at least one mode to generate an interrupt signal only if said comparison means indicates a difference and the first error signal is asserted.

Claim 10

Apparatus for use in a computer system which operates to provide error information, including a first error signal specifying that a single-bit error has occurred, a second error signal specifying that some error has occurred, a bank number field that specifies a region in memory where an error has occurred, a syndrome field where at least some values of the syndrome specify that a single-bit error has occurred in a particular sub-region of memory, comprising: register means having a data input and a clock input for storing a bank and syndrome provided at the time of the most recent previous error; means for applying the incoming bank and syndrome to said data input of said register means; comparison means for providing an indication whether the stored bank and syndrome differ from the incoming bank and syndrome; means, responsive to the second error signal, for providing a clock signal at said clock input of said register means for transferring the incoming bank and syndrome into said register means; and means for generating an interrupt signal, operable in at least one mode to generate an interrupt signal only if said comparison means indicates a difference and the first error signal is asserted.

Claim 11

The apparatus of claim 8 wherein said means for generating an interrupt is operable in at least one additional mode to generate an interrupt signal whenever said first error signal is asserted, regardless of the indication from said comparison means.

Claim 14

The method of claim 10 wherein said generating step is performed only for single-bit errors.

Claim 15

The method of claim 10, and further comprising the step of generating, in at least one additional mode, an interrupt signal whenever said at least one type of error has occurred, regardless of the indication from said comparison means.