US5093807A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video frame storage system
Assignee: Texas Instruments Inc
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Filing: 1990-04-20
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Granted: 1992-03-03
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Expires: 2010-04-20
Abstract
Abstract A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
Inventors
- 👤 Masashi Hashimoto
- 👤 Gene A. Frantz
- 👤 John V. Moravec
- 👤 Jean P. Dolait
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:50
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/391; H; H04; H04B; H04B7/00; H04B7/14; H04B7/15; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G11C7/1036; G11C7/1072; G11C7/1075; H04B7/185; H04B7/18502
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
212 words
A memory circuit for storing and reading out streams of data, the memory circuit accommodating both serial access and selected access, and the memory circuit comprising: a random access memory array having an address input and a data input port; a data buffer having a data output port coupled to the memory array data input port, the data buffer being arranged for asynchronously applying the streams of data to the memory array; an address sequencer including a first register having a data input coupled to a node which serves as the address sequencer data, said address sequencer output coupled to the memory array address input, the address sequencer generating a sequence of memory addresses to be successively applied to the memory array; a second register having an output, the second register being arranged for storing an increment step value; and an adder having a first input coupled to the first register output, a second input coupled to the second register output, and an output coupled to the first register data input; and an address buffer register having an output coupled to the address sequencer data input, the address buffer register supplying a selected address to the address sequencer data input to initialize the sequence of memory addresses generated by the address sequencer.
Claim 2
Dependent Claim
212 words
A memory circuit for storing and reading out streams of data, the memory circuit accommodating both serial access and selected access, and the memory circuit comprising: a random access memory array having an address input and a data input port; a data buffer having a data output port coupled to the memory array data input port, the data buffer being arranged for asynchronously applying the streams of data to the memory array; an address sequencer including a first register having a data input coupled to a node which serves as the address sequencer data, said address sequencer output coupled to the memory array address input, the address sequencer generating a sequence of memory addresses to be successively applied to the memory array; a second register having an output, the second register being arranged for storing an increment step value; and an adder having a first input coupled to the first register output, a second input coupled to the second register output, and an output coupled to the first register data input; and an address buffer register having an output coupled to the address sequencer data input, the address buffer register supplying a selected address to the address sequencer data input to initialize the sequence of memory addresses generated by the address sequencer.
Claim 3
Dependent Claim
23 words
A memory circuit, in accordance with claim 1, wherein the second register being arranged for storing an increment step value equal to one.
Claim 4
Dependent Claim
22 words
A memory circuit, in accordance with claim 1, wherein the greater register being arranged for storing an increment step greater than one.
Claim 5
Dependent Claim
212 words
A memory circuit for storing an reading out streams of data, said memory circuit accommodating both serial access and selected access, and the memory circuit comprising: a random access memory array having an address input and a data port; a data buffer having a data port coupled to the memory array data port, the data buffer being arranged for asynchronously applying the steams of data to the memory array; an address sequencer having a data input and having an output coupled to the memory array address input, the address sequencer generating a sequence of memory addresses to be successively applied to the memory array; an address buffer register having an output coupled to the address sequencer data input the address buffer register supplying a selected address to the address sequencer data input to initialize the sequence of memory addresses generated by the address sequencer; an address offset register for storing address offset data and having an output and an adder having a first input coupled to the address buffer register output, a second input coupled to the address offset register output, and an output coupled to a data input of the address buffer register, the adder providing the selected address representing a sum of a previous address and the address offset data.
Claim 6
Dependent Claim
212 words
A memory circuit for storing an reading out streams of data, said memory circuit accommodating both serial access and selected access, and the memory circuit comprising: a random access memory array having an address input and a data port; a data buffer having a data port coupled to the memory array data port, the data buffer being arranged for asynchronously applying the steams of data to the memory array; an address sequencer having a data input and having an output coupled to the memory array address input, the address sequencer generating a sequence of memory addresses to be successively applied to the memory array; an address buffer register having an output coupled to the address sequencer data input the address buffer register supplying a selected address to the address sequencer data input to initialize the sequence of memory addresses generated by the address sequencer; an address offset register for storing address offset data and having an output and an adder having a first input coupled to the address buffer register output, a second input coupled to the address offset register output, and an output coupled to a data input of the address buffer register, the adder providing the selected address representing a sum of a previous address and the address offset data.
Claim 7
Dependent Claim
26 words
A memory circuit, in accordance with claim 4, wherein the address offset register is arranged for storing address offset data having a value equal to one.
Claim 8
Dependent Claim
25 words
A memory circuit, in accordance with claim 4, wherein the address offset register is arranged for storing offset data having a value greater than one.
Claim 9
Dependent Claim
23 words
A memory circuit, in accordance with claim 4 wherein the address offset register is arranged for storing a variable value of offset data.
Claim 10
Dependent Claim
299 words
An integrated memory circuit for storing an reading out streams of data, the integrated memory circuit accommodating serial access and selected access, and the integrated memory circuit comprising: a random access memory array having an address input, a data input port, and a data output port; a first data buffer having a data output port coupled to the memory array data input port, the first data buffer asynchronously writing the stream of data into the memory array; a second data buffer having a data input port coupled to the memory, array data output port, the second data buffer asynchronously reading out the stream of data from the memory array; and first and second address generators wherein the first address generator generates addresses used for writing the data stream into the memory array, the second address generator generates addresses used for reading the data stream from the memory array, and each of the first and second address generators additionally comprises: a binary counter having an output coupled to the memory array address input and a data input, the binary counter being arranged for counting memory addresses to be applied to the memory array; a serially loaded address buffer register having an output coupled to the binary counter data input, the address buffer register being arranged for supplying an initial memory address to start the count of the binary counter; an address offset register having an output, the address offset register storing address offset data; and an adder having a first input coupled to the address buffer register output, a second input coupled to the address offset register output, and an output coupled to a data input of the address buffer register, the adder providing a sum of a previous address and the address offset data to the address buffer register.
Claim 11
Dependent Claim
299 words
An integrated memory circuit for storing an reading out streams of data, the integrated memory circuit accommodating serial access and selected access, and the integrated memory circuit comprising: a random access memory array having an address input, a data input port, and a data output port; a first data buffer having a data output port coupled to the memory array data input port, the first data buffer asynchronously writing the stream of data into the memory array; a second data buffer having a data input port coupled to the memory, array data output port, the second data buffer asynchronously reading out the stream of data from the memory array; and first and second address generators wherein the first address generator generates addresses used for writing the data stream into the memory array, the second address generator generates addresses used for reading the data stream from the memory array, and each of the first and second address generators additionally comprises: a binary counter having an output coupled to the memory array address input and a data input, the binary counter being arranged for counting memory addresses to be applied to the memory array; a serially loaded address buffer register having an output coupled to the binary counter data input, the address buffer register being arranged for supplying an initial memory address to start the count of the binary counter; an address offset register having an output, the address offset register storing address offset data; and an adder having a first input coupled to the address buffer register output, a second input coupled to the address offset register output, and an output coupled to a data input of the address buffer register, the adder providing a sum of a previous address and the address offset data to the address buffer register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |