US5220673A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device and method for programming critical hardware parameters
Assignee: Zilog Inc
•
Filing: 1991-08-01
•
Granted: 1993-06-15
•
Expires: 2011-08-01
Abstract
Abstract A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes. The various hardware options responsive to the hardware parameters include allowing for various bus interfaces, trimming the time constant of an analog RC circuit which provides internal bus timing strobes, switching internal timing strobes to external pads for output, switching external timing strobes from external pads to replace the internal strobes, and floating the outputs of all output pad drivers for junction leakage tests.
Inventors
- 👤 Monte J. Dalrymple
- 👤 Don Smith
- 👤 Lois F. Brubaker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4411; G11; G11C; G11C5/00; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
336 words
In an integrated circuit chip in a package with a plurality of external conductive pins connected to various nodes within said circuit, a first plurality of said pins being designated to be connected to a system bus, at least one other pin being designated to receive a system reset signal, at least one other pin being designated to receive a chip selection signal placed in time after said reset signal, and at least one other pin being designated to receive a write strobe signal placed in time after said chip selection signal, said circuit chip comprising: means including a control register for loading a digital signal existing on said first plurality of said pins into said register in response to said register receiving enabling and latching signals, said latching signal placed in time after or simultaneously with said enabling signal, means responsive to receipt of both of said reset and chip selection signals for applying said enabling signal to said register means, means responsive to receipt of said write strobe signal for applying said latching signal to said register means and for disabling said enabling signal applying means a short time later, thereby to disable loading of the register until another reset signal is received; an analog circuit generating a pulse of a measured time duration in order to provide a timed delay to other circuits on said chip; means connected to said analog circuit for setting the duration of said pulse; wherein said analog circuit includes a one-shot monostable multivibrator having permanently connected resistance and capacitance circuit elements that determine the duration of its pulse, and wherein said pulse duration setting means includes a plurality of additional capacitance elements and switching logic means, said pulse duration setting means responsive to one or more bits of the digital signal loaded in said control register for controlling the switching logic for selectively connecting said additional capacitance elements with the permanently connected capacitance element of said multivibrator circuit, thereby controlling the total effective capacitance of said multivibrator circuit.
Claim 2
Dependent Claim
336 words
In an integrated circuit chip in a package with a plurality of external conductive pins connected to various nodes within said circuit, a first plurality of said pins being designated to be connected to a system bus, at least one other pin being designated to receive a system reset signal, at least one other pin being designated to receive a chip selection signal placed in time after said reset signal, and at least one other pin being designated to receive a write strobe signal placed in time after said chip selection signal, said circuit chip comprising: means including a control register for loading a digital signal existing on said first plurality of said pins into said register in response to said register receiving enabling and latching signals, said latching signal placed in time after or simultaneously with said enabling signal, means responsive to receipt of both of said reset and chip selection signals for applying said enabling signal to said register means, means responsive to receipt of said write strobe signal for applying said latching signal to said register means and for disabling said enabling signal applying means a short time later, thereby to disable loading of the register until another reset signal is received; an analog circuit generating a pulse of a measured time duration in order to provide a timed delay to other circuits on said chip; means connected to said analog circuit for setting the duration of said pulse; wherein said analog circuit includes a one-shot monostable multivibrator having permanently connected resistance and capacitance circuit elements that determine the duration of its pulse, and wherein said pulse duration setting means includes a plurality of additional capacitance elements and switching logic means, said pulse duration setting means responsive to one or more bits of the digital signal loaded in said control register for controlling the switching logic for selectively connecting said additional capacitance elements with the permanently connected capacitance element of said multivibrator circuit, thereby controlling the total effective capacitance of said multivibrator circuit.
Claim 3
Dependent Claim
133 words
A packaged integrated circuit chip, comprising: a control register, means for loading said control register from outside the packaged chip, an analog circuit arranged to provide a pulse of a measured time duration, and means receiving said pulse for providing a timed delay to other circuits on said chip, wherein said analog circuit includes a one-shot monostable multivibrator having permanently connected resistance and capacitance circuit elements that determine the duration of its pulse, and wherein said pulse duration setting means includes a plurality of additional capacitance elements and switching logic means, said pulse duration setting means responsive to one or more bits within said control register for selectively connecting said additional capacitance elements with the permanently connected capacitance element of said multivibrator circuit, thereby controlling the total effective capacitance of said multivibrator circuit.
Claim 4
Dependent Claim
133 words
A packaged integrated circuit chip, comprising: a control register, means for loading said control register from outside the packaged chip, an analog circuit arranged to provide a pulse of a measured time duration, and means receiving said pulse for providing a timed delay to other circuits on said chip, wherein said analog circuit includes a one-shot monostable multivibrator having permanently connected resistance and capacitance circuit elements that determine the duration of its pulse, and wherein said pulse duration setting means includes a plurality of additional capacitance elements and switching logic means, said pulse duration setting means responsive to one or more bits within said control register for selectively connecting said additional capacitance elements with the permanently connected capacitance element of said multivibrator circuit, thereby controlling the total effective capacitance of said multivibrator circuit.
References Cited (Backward Citations)
US4218740A
Cited
US4099232A
Cited
US4409671A
Cited
US4265650A
Cited
US4405982A
Cited
US4628448A
Cited
US4841440A
Cited
US4653034A
Cited
US5036453A
Cited
US4931723A
Cited
US5031091A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-14 | 1996-12-14 | 1997-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-14 | 2000-12-14 | 2001-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-14 | 2004-12-14 | 2005-06-15 | $7700.00 | Window Closed / Lapsed |