Data processor having single clock pin

Claim 1

A monolythic integrated circuit microprocessor comprising: a single clock input terminal for receiving an externally generated clock signal which changes between first and second states at a predetermined frequency; timing signal generating means coupled to the single clock input terminal, for generating first and second complementary, non-overlapping timing signals having substantially the same frequency as said clock signal but delayed relative thereto by first and second predetermined skews, respectively; at least one data input terminal for receiving an externally generated input data signal; input gating means coupled to the single clock input terminal and to the one data input terminal, for latching the state of the input data signal in response to said clock signal changing from a selected one of said states to the other of said states; at least one address output terminal for providing an internally generated output address signal; and output gating means coupled to the single clock input terminal and to the one address output terminal and responsive to an internally generated address enable signal, for selectively coupling the internally generated output address signal to the one address output terminal in response to the clock signal changing to said selected one of said states from the other of said states; whereby the microprocessor latches the state of the input data signal and provides the output address signal with minimum skew relative to the clock signal.