US3753241A
Expired / Lapsed
US
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Shift register having internal buffer
Assignee: BAE Systems PLC
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Filing: 1971-11-18
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Granted: 1973-08-14
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Expires: 1991-11-18
Abstract
Abstract A shift register which includes an internal buffer for eliminating clock skew. The first and last cells of the register are driven by common clock pulses and the intermediate cells thereof and the buffer are driven by second and third clock pulses, respectively, having the same nominal rate as the common clock pulses. A plurality of such registers may be utilized in a digital data processing system where the first and last cells of the registers are all driven by the common clock pulses.
Inventors
- 👤 J Bayne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 02:28
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/007
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
113 words
A shift register including a first storage cell, a last storage cell and at least onE intermediate storage cell coupled therebetween, the combination comprising means for driving at least said first and last storage cells but not all the cells with common clock pulses, buffer means coupled to the input of at least one of the storage cells not driven by said common clock pulses, means for driving said storage cells not driven by said common clock pulses with second clock pulses having the same nominal rate as said common clock pulses, and means for driving said buffer means with third clock pulses having the same nominal rate as said common clock pulses.
Claim 2
Dependent Claim
113 words
A shift register including a first storage cell, a last storage cell and at least onE intermediate storage cell coupled therebetween, the combination comprising means for driving at least said first and last storage cells but not all the cells with common clock pulses, buffer means coupled to the input of at least one of the storage cells not driven by said common clock pulses, means for driving said storage cells not driven by said common clock pulses with second clock pulses having the same nominal rate as said common clock pulses, and means for driving said buffer means with third clock pulses having the same nominal rate as said common clock pulses.
Claim 3
Dependent Claim
35 words
A shift register according to claim 1, wherein each cell driven by said common clock pulses comprises a JK-type flip flop and each cell driven by said second clock pulses comprises a D-type flip flop.
Claim 4
Dependent Claim
92 words
A shift register according to claim 2 further including a first pair of AND gates coupling data signals to the J and K inputs of said first storage cell respectively, and a second pair of AND gates coupling the outputs of the last of said intermediate storage cells to the J and K inputs of said last storage cell of said register respectively, said first and second pair of AND gates being coupled to receive control signals whereby to control shifting data into said first and last storage cells of said register.
Claim 5
Dependent Claim
36 words
A shift register according to claim 1, wherein said buffer means comprises two AND gates and a pair of cross-coupled NOR gates, said AND gates being connected in series with respective ones of said NOR gates.
Claim 6
Dependent Claim
19 words
A shift register according to claim 4 wherein said AND gates are connected to receive said third clock pulses.
Claim 7
Dependent Claim
21 words
Digital data processing apparatus comprising a plurality of shift registers as claimed in claim 1, the registers being serially connected together.
Claim 8
Dependent Claim
35 words
Digital data processing apparatus according to claim 6 further including means for applying the same common clock pulses to each register when required and for interrupting said common clock pulses when they are not required.
Claim 9
Dependent Claim
25 words
A shift register according to claim 1 wherein at least one of said second and third clock pulses are time-related to said common clock pulses.
Claim 10
Dependent Claim
25 words
A shift register according to claim 1 wherein at least one of said second and third clock pulses are logically-related to said common clock pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |