US4653034A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Remote monitor unit
Assignee: United States Department of the Navy
•
Filing: 1985-11-04
•
Granted: 1987-03-24
•
Expires: 2005-11-04
Abstract
Abstract A remote monitor unit comprising a battery pack, a regulated power supply, a program control board, a receiver AD board, a plurality of memory boards and a transducer, all housed in a water tight enclosure. External control or data communication links are unnecessary with the remote monitor unit. Once the device has been activated and placed in its housing, a programmable time delay feature allows the user to place the unit at a selected site in advance of the start of the recording period without wasting any data storage capability. When deployed and activated, analog data from the transducer is converted to digital form and silently recorded by storing it in a non-volatile memory medium on the memory boards. The digitized information is later retrieved from the memory boards by micro, mini or main frame computer and stored on magnetic tape for subsequent processing. The memory boards are then erased by exposure to ultra-violet light and reused.
Inventors
- 👤 Dale H. Hoover
- 👤 Lynn A. Poole
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11B; G11B20/00; G11B20/10; G11B20/10527; G11C5/00; G11C5/14; G11C7/00; G11C7/16
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
558 words
An apparatus for receiving and silently storing acoustic signals from a remote source comprising: transducer means, for sensing and converting said acoustic signals into corresponding analog electrical signals; analog-to-digital (A/D) converter means, attached to said transducer means, for receiving said analog electrical signals, converting said analog electrical signals to corresponding digital data signals L 1 -THEX and transmitting said digital signals, said A/D converter means further providing a strobe pulse, first system clock pulses φ 1 and second system clock pulses φ 2 . main program and time delay means, connected to said A/D converter means, for receiving said φ 1 , φ 2 , strobe and data outputs therefrom and controlling the storage of said data therewith, said main program and time delay means further comprising programmable time delay means, for receiving said first clock pulse φ 1 and transmitting said first clock pulse after a preselected time delay, strobe gate means, for receiving said strobe pulse from said A/D converter means and said φ 1 pulse from said time delay means and producing first and second output pulses therefrom, a temporary data register, connected to said strobe gate means and said A/D converter means, for receiving and storing said L 1 -THEX data from said A/D converter means upon receiving said first output of said strobe gate means, memory programming control means, connected to said strobe gate means and said A/D converter means, for receiving said second output of said strobe gate means and said φ 2 pulse from said A/D converter means, and producing address select and data storage outputs therefrom, and memory address select means, connected to said memory programming control means, for sequentially selecting addresses for storage of said L 1 -THEX data; non-volatile memory means, connected to said main program and time delay means, for receiving said address select and data storage outputs from said memory programming control means, and said sequential addresses from said memory address select means and selectively storing by burning in said data received therefrom, said non-volatile memory means further comprising a plurality of memory boards, each said memory board having an input buffer as an integral part thereof; power supply means, connected to said A/D converter means, said main program means and said memory means, for controllably supplying preselected voltages thereto, said power supply means further comprising, a battery pack, for producing an 8 volt output and a 36 volt output, and voltage regulating means, connected to said battery pack 8 volt and 36 volt outputs, said A/D converter means, said main program means and said memory means, for producing a 25 volt output and a pair of 5 volt outputs respectively therefrom, said 25 volt output feeding said memory means, one said 5 volt output feeding each memory input buffer and the other said 5 volt output powering said A/D converter means and said main program means; and watertight housing means, enclosing said transducer means, said A/D converter means, said main program means, said memory means and said power supply means, for providing a watertight enclosure for said transducer means, said A/D coverter means, said main program means, said memory means and said power supply while exposing said transducer means to said acoustic field; said apparatus operating so as to perform said data sensing and storage such that no self-noise produced thereby contaminates said acoustic signals.
Claim 2
Independent Claim
558 words
An apparatus for receiving and silently storing acoustic signals from a remote source comprising: transducer means, for sensing and converting said acoustic signals into corresponding analog electrical signals; analog-to-digital (A/D) converter means, attached to said transducer means, for receiving said analog electrical signals, converting said analog electrical signals to corresponding digital data signals L 1 -THEX and transmitting said digital signals, said A/D converter means further providing a strobe pulse, first system clock pulses φ 1 and second system clock pulses φ 2 . main program and time delay means, connected to said A/D converter means, for receiving said φ 1 , φ 2 , strobe and data outputs therefrom and controlling the storage of said data therewith, said main program and time delay means further comprising programmable time delay means, for receiving said first clock pulse φ 1 and transmitting said first clock pulse after a preselected time delay, strobe gate means, for receiving said strobe pulse from said A/D converter means and said φ 1 pulse from said time delay means and producing first and second output pulses therefrom, a temporary data register, connected to said strobe gate means and said A/D converter means, for receiving and storing said L 1 -THEX data from said A/D converter means upon receiving said first output of said strobe gate means, memory programming control means, connected to said strobe gate means and said A/D converter means, for receiving said second output of said strobe gate means and said φ 2 pulse from said A/D converter means, and producing address select and data storage outputs therefrom, and memory address select means, connected to said memory programming control means, for sequentially selecting addresses for storage of said L 1 -THEX data; non-volatile memory means, connected to said main program and time delay means, for receiving said address select and data storage outputs from said memory programming control means, and said sequential addresses from said memory address select means and selectively storing by burning in said data received therefrom, said non-volatile memory means further comprising a plurality of memory boards, each said memory board having an input buffer as an integral part thereof; power supply means, connected to said A/D converter means, said main program means and said memory means, for controllably supplying preselected voltages thereto, said power supply means further comprising, a battery pack, for producing an 8 volt output and a 36 volt output, and voltage regulating means, connected to said battery pack 8 volt and 36 volt outputs, said A/D converter means, said main program means and said memory means, for producing a 25 volt output and a pair of 5 volt outputs respectively therefrom, said 25 volt output feeding said memory means, one said 5 volt output feeding each memory input buffer and the other said 5 volt output powering said A/D converter means and said main program means; and watertight housing means, enclosing said transducer means, said A/D converter means, said main program means, said memory means and said power supply means, for providing a watertight enclosure for said transducer means, said A/D coverter means, said main program means, said memory means and said power supply while exposing said transducer means to said acoustic field; said apparatus operating so as to perform said data sensing and storage such that no self-noise produced thereby contaminates said acoustic signals.
Claim 3
Dependent Claim
19 words
An apparatus according to claim 1 wherein said programmable time delay means is a Dual Inline Package (DIP) switch.
Claim 4
Dependent Claim
91 words
An apparatus according to claim 2 wherein said memory programming control means further comprises: a timing clock gate, connected to said strobe gate, for receiving said strobe signal and said φ 2 input from said A/D converter means; program control logic means, connected to said timing clock gate, for receiving the output thereof and producing as output signals, an incrementing pulse, VE, CE, and OE/DE in response thereto; and memory incrementing logic, connected to said program control logic means for receiving said incrementing pulse and incrementing said memory address select means.
Claim 5
Dependent Claim
88 words
An apparatus according to claim 3 wherein said memory address select means further comprises: a memory board select register, connected to said memory incrementing logic, for receiving the incrementing pulse therefrom and sequentially selecting a memory board therewith; a chip select register, connected to said memory incrementing logic and said memory board select register, for sequentially selecting a desired memory chip; and a chip address register connected to said memory incrementing logic and said chip select register, for sequentially selecting a desired address on a chosen memory chip.
References Cited (Backward Citations)
US4480323A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |