Semiconductor memory device supporting cache and method of driving the same

Claim 2

A semiconductor memory device integrated on a semiconductor chip (500), comprising; a DRAM cell array (300) including a plurality of dynamic type memory cells arranged in a matrix of rows and columns, said DRAM cell array including a plurality of blocks (300') each having a group of columns, an SRAM cell array (310) including a plurality of static type memory cells (SMC) arranged in a matrix of rows and columns, said SRAM cell array including a plurality of blocks (18) corresponding to said blocks of said DRAM cell array, transfer means (330; 17) for transferring data in a block between said DRAM cell array and said SRAM cell array, store/detect means (320; 340) for storing addresses of data stored in said blocks of said SRAM cell array, and detecting match/mismatch between an externally supplied first address signal and an address stored therein (320; 340), first means (20, 22, 23, 27, 29, 370, 380, 390) responsive to a match detection signal from said store/detect means and an externally supplied second address signal for selecting a corresponding memory cell from said SRAM cell array and connecting said corresponding memory cell to an internal data transmission line (I/O, I/O), and second means (350, 360, 380, 20) responsive to a mismatch detection signal from said store/detect means and said first and second addresses for selecting a corresponding memory cell from said DRAM cell array and connecting that memory cell to said internal data transmission line through a column of said SRAM array.

Claim 3

A memory device according to claim 1, wherein said first means includes; means (380) responsive to said second address signal for generating an SRAM word line drive signal (SWL1-SWL4) for selecting a row in said SRAM cell array, and means (29) responsive to said match detection signal from said store/detect means for directly transmitting said SRAM word line drive signal to an SRAM word line connecting memory cells of one row of the SRAM cell array for which a match is detected.

Claim 4

A memory device according to claim 1, wherein said first means includes; means (340) responsive to said first address signal for generating an internal row designating signal for designating a row in said DRAM cell array, and applying at least a part of said internal row designating signal to said store/detect means as an address for retrieval, means (370) responsive to said second address signal for generating internal column designating signal for designating a column in said DRAM cell array, said first address signal and said second address signal being externally applied at substantially the same timing, column/block selecting means (380, 390) responsive to said internal column designating signal for generating signals for selecting a column and a block in said DRAM cell array, respectively, and means (410) for causing said store/detect means and said column/block selecting means to operate parallel to each other.

Claim 5

A memory device according to claim 1 wherein said store/detect means includes; a plurality of match detection lines (23-1 to 23-4) extending in one direction, a plurality of data input lines (X0-X11, X0-X11) extending in a direction crossing said match detection lines for receiving respective bits corresponding to said first address signal, a plurality of content addressable memories (CAM11-CAM124) arranged at respective crossings between said match detection lines and said data input lines, content addressable memories on one row connected to a single match detection line storing an address for data stored in said SRAM cell array, and a plurality of CAM word lines (CWL1-CWL4) extending in said one direction, said content addressable memories on each respective row being connected to a corresponding CAM word line, said content addressable memories being arranged in rows and columns to correspond to said rows and columns in said SRAM cell array, and said match/mismatch detection signal being transmitted to said match detection lines for application to said first means.

Claim 6

A memory device according to claim 1, wherein said store/detect means is provided for each block in said SRAM cell array for detecting match/mismatch of address in relation to each block in said SRAM cell array.

Claim 7

A memory device according to claim 1, wherein said store/detect means includes means (22) responsive to a potential of said second address signal and a potential on a signal line connecting a row in said SRAM cell array for transmitting said mismatch detection signal to said second means.

Claim 8

A memory device according to claim 1, wherein said DRAM cell array includes n columns (31, 32, 33, 34) for each column (40) in said SRAM cell array, said SRAM cell array including SRAM cells arranged in n rows, n being an integer.

Claim 9

A memory device according to claim 7, wherein said second means includes means (380, 390, 330, 17) responsive to said mismatch detection signal for connecting one of said n rows in said DRAM cell array block to a corresponding column in said SRAM cell array block.

Claim 10

A memory device according to claim 1, wherein said second means includes; means (395) responsive to said externally applied second address signal for generating a first column detecting signal for selecting a column in said SRAM cell array, and means (410, 350, 360, 29, 17) responsive to said mismatch detection signal from said store/detect means for temporarily disregarding said external applied first address signal, and responsive to said first column selecting signal for reading from said store/detect means an address corresponding to said SRAM cell array column designated by said first column selecting signal, selecting a corresponding memory cell in said DRAM cell array in response to thus read out address, reading memory cell data in a designated column in said SRAM cell array in response to said first column selecting signal, and writing the data read from the SRAM cell to said selected corresponding, dynamic memory cell through said transfer means.

Claim 11

A semiconductor memory device comprising; a DRAM cell array (300) including a plurality of dynamic type memory cells (DMC) arranged in a matrix of rows and columns, said DRAM cell array being divided into a plurality of blocks (300,) each having a group of columns, said DRAM cell array including a plurality of DRAM word lines (WL) each having dynamic type memory cells on one row connected, and a plurality of DRAM bit lines (BL, BL) each having dynamic type memory cells on one column connected, an SRAM cell array (310) including a plurality of static type memory cells (SMC) arranged in a matrix of rows and columns, said SRAM cell array being divided into a plurality of blocks (18) corresponding to said blocks of said DRAM cell array, each of said blocks of said SRAM cell array including a plurality of SRAM word lines (SWL) each having static type memory cells of one row in said blocks connected, and a plurality of SRAM bit lines (40) each having static type memory cells of one column connected, a CAM cell array (320) including a plurality of content addressable memories (CMC) arranged in a matrix of rows and columns, said CAM cell array having a plurality of blocks corresponding to said blocks of said SRAM cell array, each of said CAM cell array blocks having a plurality of CAM word lines (CWL) each having content addressable memory cells of one row in the blocks connected, a plurality of data input lines (X0-X11, X11) each having addressable memory cells of one column are connected, and a plurality of local match lines each having content addressable memory cells of one row in the blocks connected, a plurality of drive means (29) each disposed between each respective said SRAM cell array block and each respective said CAM cell array block, and each for directly driving an SRAM word line in the associated block to place the SRAM word line in a selected state in response to a signal potential on the local match line in the associated block, a plurality of cache hit/miss signal generating means (22) associated with respective said SRAM cell array blocks, for generating a signal indicating a cache hit/miss in response to a signal potential on the SRAM word line in each respective associated block, means (340) responsive to an externally applied first address signal for generating a first internal address signal for designating a row in said DRAM cell array, and applying at least a part of said first internal address signal to said CAM cell array blocks as a retrieval data, means (390) responsive to an externally applied second address signal for generating a block selecting signal, means (22) responsive to said block selecting signal for activating a corresponding CAM cell array block, means (380) responsive to said second address signal for generating a signal for selecting a column in said DRAM cell array and in said SRAM cell array, means (Tr1, Tr2, 19, 420) responsive to the cache hit indicating signal and said column selecting signal for connecting the selected column in said SRAM cell array to circuitry external to said semiconductor memory device, and means (350, 360, 380, 395, 420) responsive to the cache miss indicating signal, said column selecting signal and said first address signal for connecting a memory cell in the selected row and column in said DRAM cell array to circuitry external to said semiconductor memory device through associated column in said SRAM cell array.

Claim 12

A semiconductor memory device comprising; a DRAM cell array (300) including a plurality of dynamic type memory cells (DMC) arranged in a matrix of rows and columns, said DRAM cell array being divided into a plurality of blocks (300,) each having a group of columns, said DRAM cell array including a plurality of DRAM word lines (WL) each having dynamic type memory cells on one row connected, and a plurality of DRAM bit lines (BL, BL) each having dynamic type memory cells on one column connected, an SRAM cell array (310) including a plurality of static type memory cells (SMC) arranged in a matrix of rows and columns, said SRAM cell array being divided into a plurality of blocks (18) corresponding to said blocks of said DRAM cell array, each of said blocks of said SRAM cell array including a plurality of SRAM word lines (SWL) each having static type memory cells of one row in said blocks connected, and a plurality of SRAM bit lines (40) each having static type memory cells of one column connected, a CAM cell array (320) including a plurality of content addressable memories (CMC) arranged in a matrix of rows and columns, said CAM cell array having a plurality of blocks corresponding to said blocks of said SRAM cell array, each of said CAM cell array blocks having a plurality of CAM word lines (CWL) each having content addressable memory cells of one row in the blocks connected, a plurality of data input lines (X0-X11, X11) each having addressable memory cells of one column are connected, and a plurality of local match lines each having content addressable memory cells of one row in the blocks connected, a plurality of drive means (29) each disposed between each respective said SRAM cell array block and each respective said CAM cell array block, and each for directly driving an SRAM word line in the associated block to place the SRAM word line in a selected state in response to a signal potential on the local match line in the associated block, a plurality of cache hit/miss signal generating means (22) associated with respective said SRAM cell array blocks, for generating a signal indicating a cache hit/miss in response to a signal potential on the SRAM word line in each respective associated block, means (340) responsive to an externally applied first address signal for generating a first internal address signal for designating a row in said DRAM cell array, and applying at least a part of said first internal address signal to said CAM cell array blocks as a retrieval data, means (390) responsive to an externally applied second address signal for generating a block selecting signal, means (22) responsive to said block selecting signal for activating a corresponding CAM cell array block, means (380) responsive to said second address signal for generating a signal for selecting a column in said DRAM cell array and in said SRAM cell array, means (Tr1, Tr2, 19, 420) responsive to the cache hit indicating signal and said column selecting signal for connecting the selected column in said SRAM cell array to circuitry external to said semiconductor memory device, and means (350, 360, 380, 395, 420) responsive to the cache miss indicating signal, said column selecting signal and said first address signal for connecting a memory cell in the selected row and column in said DRAM cell array to circuitry external to said semiconductor memory device through associated column in said SRAM cell array.

Claim 15

A method according to claim 11, wherein the step of generating said second internal address signal is carried out in parallel with the retrieval operation in said CAM cell array.

Claim 16

A method according to claim 11, further including the steps of selecting a row and a column in said DRAM cell array, selecting a column in said SRAM cell array, and connecting a memory cell at a crossing between the selected row and column in said DRAM cell array to circuitry external to said semiconductor memory device through the selected column in said SRAM cell array in response to said first and second internal address signals and said cache hit/miss indicating signal.

Claim 17

A method according to claim 11 further comprising the steps of; generating a third internal address signal for selecting a row in said SRAM cell array in response to said second address signal, generating a signal for selecting a row in said CAM cell array in response to said cache hit/miss indicating signal and said second address signal, reading contents of the selected row in said CAM cell array in response to said cache hit/miss indicating signal and said CAM cell array row selecting signal, selecting a row in said DRAM cell array in response to the read out content of said CAM cell array, and writing the content of the selected row in said CAM cell array to memory cells in said selected row in said DRAM cell array in response to said third internal address signal.

Claim 18

A method according to claim 11, wherein said DRAM cell array, said SRAM cell array and said CAM cell array each include a plurality of blocks, said blocks in one array being in a one-to-one relationship with said blocks in the other arrays, and wherein said method includes the steps of generating a signal for selecting a block in response to said second address signal, and executing all said mentioned steps for the block selected by said block selecting signal.