Abstract The present invention provides a memory addressing system that can accommodate multiple size DRAMS. DRAMS of various sizes can be mixed in a variety of ways. The present invention provides a hardware register associated with each pair of banks of DRAMS. This hardware register is programmable to indicate the type of DRAMS that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks. Using this technique, it is necessary to insert the largest memory chips in the first memory bank. Memory chips of either size can be inserted in either set of memory banks and the information in the programmable register is used to control circuitry which appropriately modifies the accessing signals which are sent to the memory system.
A memory accessing system for a memory that has a plurality of physical memory banks of DRAMS having a first size and a second size with a nonvolatile memory associated with the accessing system for storing data indicating the size of the DRAMS in said physical memory banks, comprising: means for supplying address signals to said memory banks and for generating row and column accessing signals for said memory; a hardware configuration register; means for transferring information from the nonvolatile memory to said configuration register to indicate which of said first and second sizes of DRAMS have been inserted in the particular memory banks; and logic means, having inputs coupled to said means for supplying address signals and said configuration register, for using the information in said configuration register to modify said row and column accessing signals.
Claim 2
Dependent Claim
137 words
A memory accessing system for a memory that has a plurality of physical memory banks of DRAMS having a first size and a second size with a nonvolatile memory associated with the accessing system for storing data indicating the size of the DRAMS in said physical memory banks, comprising: means for supplying address signals to said memory banks and for generating row and column accessing signals for said memory; a hardware configuration register; means for transferring information from the nonvolatile memory to said configuration register to indicate which of said first and second sizes of DRAMS have been inserted in the particular memory banks; and logic means, having inputs coupled to said means for supplying address signals and said configuration register, for using the information in said configuration register to modify said row and column accessing signals.