US4835733A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable access memory
Assignee: STMicroelectronics lnc USA
•
Filing: 1985-09-30
•
Granted: 1989-05-30
•
Expires: 2005-09-30
Abstract
Abstract An integrated circuit memory includes processing capability on the same chip, on one or both of an address path and data path between a set of access registers and a memory array so that an address can be generated, checked or manipulated and/or data can be manipulated or compared with a reference pattern of data.
Inventors
- 👤 Jon Powell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:41
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1441
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
289 words
An integrated circuit memory system on a single chip having at least one control unit and comprising: an array (200) of memory cells; decoder means responsive to a memory address for accessing at least one selected cell within said array (200); a set of access registers (100) for storing memory address data and memory data; a programmed access register controller means (120), responsive to external control signals (30), for controlling said set (100) of access registers; and a switchable network (50) of conductors connecting said array of memory cells with said set (100) of access registers; characterized in that said system further includes: at least one additional access register within said set (100) for storing at least one mode parameter and control parameters; address generation means (300) for generating a current memory address from an input reference signal (10) and being connected in an address data path (40, 42, 44) between said set (100) of access registers and said array (200) of memory cells to apply said current memory address to said decoder means, said address generation means including means for automatically incrementing a current address through a predetermined address range as successive data are stored, whereby a block of data in said predetermined address range may be stored without repeated address inputs; and data path controller means (150) coupled to and controlling, under stored program control (510, 520), said address generation means (300) and said switchable network (50) of conductors sequentially in a selected one of at least two different memory modes of operation specified by at least one mode parameter stored in said set of access registers, whereby said array (200) of memory cells may be logically structured, selectively, as at least two different types of memory.
Claim 2
Dependent Claim
289 words
An integrated circuit memory system on a single chip having at least one control unit and comprising: an array (200) of memory cells; decoder means responsive to a memory address for accessing at least one selected cell within said array (200); a set of access registers (100) for storing memory address data and memory data; a programmed access register controller means (120), responsive to external control signals (30), for controlling said set (100) of access registers; and a switchable network (50) of conductors connecting said array of memory cells with said set (100) of access registers; characterized in that said system further includes: at least one additional access register within said set (100) for storing at least one mode parameter and control parameters; address generation means (300) for generating a current memory address from an input reference signal (10) and being connected in an address data path (40, 42, 44) between said set (100) of access registers and said array (200) of memory cells to apply said current memory address to said decoder means, said address generation means including means for automatically incrementing a current address through a predetermined address range as successive data are stored, whereby a block of data in said predetermined address range may be stored without repeated address inputs; and data path controller means (150) coupled to and controlling, under stored program control (510, 520), said address generation means (300) and said switchable network (50) of conductors sequentially in a selected one of at least two different memory modes of operation specified by at least one mode parameter stored in said set of access registers, whereby said array (200) of memory cells may be logically structured, selectively, as at least two different types of memory.
Claim 3
Dependent Claim
41 words
A memory system according to claim 1, further characterized in that said address generation means generates a current address for storing data by operating on a START address and in which said current address is stored in a WRITE pointer register.
Claim 4
Dependent Claim
30 words
A memory system according to claim 2, in which said address generation means includes means for generating current addresses for a FIFO memory logical structure embodied in said memory system.
Claim 5
Dependent Claim
30 words
A memory system according to claim 2, in which said address generation means includes means for generating current addresses for a LIFO memory logical structure embodied in said memory system.
Claim 6
Dependent Claim
57 words
A memory system according to claim 1, in which said address generation means includes means for generating a series of read addresses within a first address range and a related series of write addresses within a second address range, in the course of a predetermined data transfer sequence controlled under stored program control by said controller means.
Claim 7
Dependent Claim
91 words
An integrated circuit memory system according to claim 1, in which said programmed access register controller (120) responds to a predetermined pattern of mode control signals to select a stored program (1510) within said data path controller means (150) for operating said address generation means (300) in a predetermined mode to calculate a current value for a memory address register (320); and said programmed access register controller (120) responds to external control signals to initiate selected sequences of instructions within said stored program (1510) in said data path controller means (150).
Claim 8
Dependent Claim
192 words
An integrated circuit memory system on a single chip having at least one control unit and comprising: an array (200) of memory cells; decoder means responsive to a memory address for accessing at least one selected cell within said array (200); a set of access registers (100) connected to at least one input/output terminal for storing memory address, memory data, mode and control parameters; a switchable network (50) of conductors connecting said array of memory cells with said set (100) of access registers; address logical operation means (400) connected between said set of access registers and said array of memory cells for performing, in response to an input signal, a logical operation on a current memory address, said address logical operation means (400) including means for comparing a current memory address with at least one reference address to determine if said current address is within a permitted range; and controller means for controlling said address logical operation means and said switchable network (50) of conductors in a selected one of at least two different memory modes of operation specified by at least one mode parameter stored in said set of access registers.
Claim 9
Dependent Claim
192 words
An integrated circuit memory system on a single chip having at least one control unit and comprising: an array (200) of memory cells; decoder means responsive to a memory address for accessing at least one selected cell within said array (200); a set of access registers (100) connected to at least one input/output terminal for storing memory address, memory data, mode and control parameters; a switchable network (50) of conductors connecting said array of memory cells with said set (100) of access registers; address logical operation means (400) connected between said set of access registers and said array of memory cells for performing, in response to an input signal, a logical operation on a current memory address, said address logical operation means (400) including means for comparing a current memory address with at least one reference address to determine if said current address is within a permitted range; and controller means for controlling said address logical operation means and said switchable network (50) of conductors in a selected one of at least two different memory modes of operation specified by at least one mode parameter stored in said set of access registers.
Claim 10
Dependent Claim
73 words
An integrated circuit memory system according to claim 7, in which said at least two memory modes include a stack mode in which said memory system functions as a LIFO stack having a stack pointer, starting address and data register within said set of access registers; in which a current value of said stack pointer is calculated by address calculation means within said address logical operation means under control of said controller means.
Claim 11
Dependent Claim
43 words
An integrated circuit memory system according to claim 7, in which said address logical operation means compares a current memory address with an upper reference address and with a lower reference address to determine if said current address is within a permitted range.
Claim 12
Dependent Claim
78 words
An integrated circuit memory system according to claim 7, in which said address logical operation means compares a current memory address with at least one reference address to determine if said current address is with a permitted range and, if said current address is greater than an upper bound of said address range, said address logical operation means substitutes for said current address a predetermined lower bound address, so that said memory system functions as a circular buffer.
Claim 13
Dependent Claim
78 words
An integrated circuit memory system according to claim 7, in which said address logical operation means compares a current memory address with at least one reference address to determine if said current address is within a permitted range and, if said current address is less than a lower bound of said address range, said address logical operation means substitutes for said current address a predetermined upper bound address, so that said memory system functions as a circular buffer.
Claim 14
Dependent Claim
236 words
An integrated circuit memory system comprising: a set (100) of access registers for storing memory addresses, memory data, and control parameters; a memory unit comprising an array (200) of memory cells having decoder means connected thereto and a RAM controller (220) coupled to and controlling said decoder and memory array; data path controller means (150) responsive to a set of parameters including mode control parameters (530), for controlling the operation of a first data path (40, 42, 44) for transmitting memory addresses from said set (100) of access registers to said decoder means of said memory unit (200) and a second data path (46, 40) for passing memory data to and from said set (100) of access registers and said memory unit (200), which data path controller means (150) contains stored program control means (1520) and means (50) for controlling said first and second data paths; and data manipulation means (500), located on said second data path (46, 40) and connected between said set (100) of access registers and said memory unit (200) and under stored program control (1510), for selectively manipulating, modifying, and identifying data passing between said set (100) of access registers and said memory unit (200), said data manipulation means altering data that is passing on said second data path (46, 40) between said set (100) of access registers and said memory unit (200) by performing a logical operation on said passing data.
Claim 15
Dependent Claim
236 words
An integrated circuit memory system comprising: a set (100) of access registers for storing memory addresses, memory data, and control parameters; a memory unit comprising an array (200) of memory cells having decoder means connected thereto and a RAM controller (220) coupled to and controlling said decoder and memory array; data path controller means (150) responsive to a set of parameters including mode control parameters (530), for controlling the operation of a first data path (40, 42, 44) for transmitting memory addresses from said set (100) of access registers to said decoder means of said memory unit (200) and a second data path (46, 40) for passing memory data to and from said set (100) of access registers and said memory unit (200), which data path controller means (150) contains stored program control means (1520) and means (50) for controlling said first and second data paths; and data manipulation means (500), located on said second data path (46, 40) and connected between said set (100) of access registers and said memory unit (200) and under stored program control (1510), for selectively manipulating, modifying, and identifying data passing between said set (100) of access registers and said memory unit (200), said data manipulation means altering data that is passing on said second data path (46, 40) between said set (100) of access registers and said memory unit (200) by performing a logical operation on said passing data.
Claim 16
Dependent Claim
51 words
An integrated circuit memory system according to claim 12, in which said data manipulation means alters data that is passing on said second data path between said set of access registers and said memory unit by performing a logical operation using said passing data and a predetermined set of modifying data.
Claim 17
Dependent Claim
31 words
An integrated circuit memory system according to claim 12, in which said data manipulation means operates to compare data on said second data path with a predetermined reference pattern of data.
Claim 18
Dependent Claim
53 words
An integrated circuit memory system according to claim 14, in which said data manipulation means operates to compare data passing out of said memory array on said second data path with a predetermined reference pattern of data and generates an identifying signal when a match is found with said reference pattern of data.
Claim 19
Dependent Claim
62 words
An integrated circuit memory system according to claim 15, further including an address generation means that steps a current memory address through a predetermined address range and in which said data path controller means reads out the contents of said current memory address to said data manipulation means until a match is found, whereby said memory system operates as a content-addressable memory.
Claim 20
Dependent Claim
53 words
An integrated circuit memory system according to claim 16, in which the contents of a predetermined range of memory addresses relative to said current address are read out in response to said identifying match signal, whereby a block of data of predetermined size may be located by a search on one element thereof.
Claim 21
Dependent Claim
54 words
An integrated circuit memory system according to claim 16, in which stored data are written into a predetermined range of memory addresses relative to said current address in response to said identifying match signal, whereby a block of data of predetermined size may be located and altered by a search on one element thereof.
Claim 22
Dependent Claim
60 words
An integrated circuit memory system according to claim 12, further including an address generation means (300) for stepping through a predetermined memory address range; in which said data path controller means operates on said first data path at selected addresses within said address range, whereby that data passing on said first data path is affected by said data manipulation means.
Claim 23
Dependent Claim
40 words
An integrated circuit memory system according to claim 19, in which said data manipulation means imposes stored data on said second data path during a read operation, so that said predetermined memory address range is filled with said stored data.
Claim 24
Dependent Claim
16 words
An integrated circuit memory system according to claim 20, in which said stored data is fixed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-29 | 1992-11-28 | 1993-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-29 | 1996-11-28 | 1997-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-29 | 2000-11-28 | 2001-05-30 | $7700.00 | Window Closed / Lapsed |