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US4752915A Expired / Lapsed US ⏱️ 0.0 years remaining

Two dimensionally addressable memory apparatus with bank switching

Assignee: Hitachi Ltd
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Filing: 1985-08-16
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Granted: 1988-06-21
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Expires: 2005-08-16
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Abstract

Abstract A memory apparatus is managed by two-dimensional addresses consisting of X and Y addresses and is divided into a plurality of memory banks. One of the memory banks is selected by lower significant bits including the least significant bit in each of the X and Y addresses. A different memory bank is selected by the updating of the X address or by the updating of the Y address.

Inventors

  • 👤 Kenji Suzuki
  • 👤 Hiroshi Mochizuki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 18:26
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 107 words
A memory apparatus which is managed by two-dimensional addresses consisting of X and Y addresses, comprising: a memory divided into a plurality of memory banks; address registers into which X and Y addresses to access each of said memory banks of said memory are set; and bank switching control means for selecting one of said memory banks, including an exclusive OR gate connected to receive the least significant bit in each of said X and Y addresses and selection means for selecting a different memory bank in response to an output of said exclusive OR gate whenever either one of the X and Y addresses is changed.
Claim 2
Dependent Claim 107 words
A memory apparatus which is managed by two-dimensional addresses consisting of X and Y addresses, comprising: a memory divided into a plurality of memory banks; address registers into which X and Y addresses to access each of said memory banks of said memory are set; and bank switching control means for selecting one of said memory banks, including an exclusive OR gate connected to receive the least significant bit in each of said X and Y addresses and selection means for selecting a different memory bank in response to an output of said exclusive OR gate whenever either one of the X and Y addresses is changed.

References Cited (Backward Citations)

US3916169A Cited
US4051457A Cited
US4074254A Cited
US4153950A Cited
US4410965A Cited
US4585220A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-06-21 1991-12-21 1992-06-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-06-21 1995-12-21 1996-06-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-06-21 1999-12-21 2000-06-21 $7700.00 Window Closed / Lapsed

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