US3916169A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Calculator system having a precharged virtual ground memory
Assignee: Texas Instruments Inc
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Filing: 1973-09-13
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Granted: 1975-10-28
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Expires: 1993-09-13
Abstract
Abstract Disclosed is a calculator featuring a virtual ground permanent store instruction memory for storing and providing instruction words. The memory cells are arrayed in rows and columns which are respectively responsive to row and column address circuits. Each bit of the instruction word is outputted on a single output line, and a pair of output lines have only one ground line selectively coupling each to circuit ground. The row and column lines are precharged by decoupling the ground lines from circuit ground and precharging the respective output lines, with the column address circuitry coupling each column line to the respective output line for precharging all columns.
Inventors
- 👤 Michael J Cochran
- 👤 Jr Charles P Grant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:22
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/126
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
207 words
In a data processing system of the type implemented on at least one semiconductor chip and having a virtual ground, permanent store programm memory for storing and selectively providing instruction words in response to an address signal, the memory comprising: a. rows and columns of memory cells having columns grouped to provide a plurality of bits forming the instruction word, and rows addressable to define the bits of the instruction word; b. one output line corresponding to each bit of the instruction word; c. precharging switch means, connected to the output lines for precharging the output lines; d. transfer switch means for connecting the output lines to the columns of memory cells for precharging all columns; e. row select circuitry, responsive to the address signal, for selectively activating rows of the array; f. column select circuitry, responsive to the address signal, selectively activating a column of memory cells by coupling the substrate potential to the selected column and by coupling the corresponding output line to the selected column; and g. timing means, for activating the precharging and transfer switch means for a first prEdetermined time period and for activating the row and column select circuitry for a second predetermined time period following the first predetermined time period.
Claim 2
Dependent Claim
207 words
In a data processing system of the type implemented on at least one semiconductor chip and having a virtual ground, permanent store programm memory for storing and selectively providing instruction words in response to an address signal, the memory comprising: a. rows and columns of memory cells having columns grouped to provide a plurality of bits forming the instruction word, and rows addressable to define the bits of the instruction word; b. one output line corresponding to each bit of the instruction word; c. precharging switch means, connected to the output lines for precharging the output lines; d. transfer switch means for connecting the output lines to the columns of memory cells for precharging all columns; e. row select circuitry, responsive to the address signal, for selectively activating rows of the array; f. column select circuitry, responsive to the address signal, selectively activating a column of memory cells by coupling the substrate potential to the selected column and by coupling the corresponding output line to the selected column; and g. timing means, for activating the precharging and transfer switch means for a first prEdetermined time period and for activating the row and column select circuitry for a second predetermined time period following the first predetermined time period.
Claim 3
Dependent Claim
44 words
The memory of claim 1 wherein the array comprises one substrate potential line per pair of output lines, each substrate potential line being selectively coupled to its respective pair of output lines through a pair of cell columns selected by the column select circuitry.
Claim 4
Dependent Claim
21 words
The memory of claim 2 wherein the substrate potential line is selectively coupled to the substrate potential through a gating element.
Claim 5
Dependent Claim
41 words
The memory of claim 3 further comprising discharge means, connected to the row and column circuitry and selectively coupled to the substrate potential, for discharging the row and column circuitry prior to the first predetermined time period, thereby precharging all rows.
Claim 6
Dependent Claim
41 words
The memory of claim 1 further comprising discharge means, connected to the row and column circuitry and selectively coupled to the substrate potential, for discharging the row and column circuitry prior to the first predetermined time period, thereby precharging all rows.
Claim 7
Dependent Claim
24 words
The memory of claim 5 wherein the row select circuitry comprises gating elements responsive to the address signal for selectively discharging one precharged row.
Claim 8
Dependent Claim
24 words
The memory of claim 1 wherein the row select circuitry comprises gating elements responsive to the address signal for selectively discharging one precharged row.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-27 | 1979-04-28 | 1979-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-27 | 1983-04-28 | 1983-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-27 | 1987-04-28 | 1987-10-28 | $7700.00 | Window Closed / Lapsed |