US3728696A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density read-only memory
Assignee: Boeing North American Inc
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Filing: 1971-12-23
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Granted: 1973-04-17
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Expires: 1991-12-23
Abstract
Abstract A read-only memory (ROM) has a plurality of address input lines and selection lines forming a matrix with regions of a semiconductor substrate. Binary information is stored at locations between adjacent semiconductor regions by the presence or absence of field effect transistors thereat. Alternate semiconductor regions are selectively connected to a voltage reference, and the remaining regions there-between are selectively connected to a common output point by means of selection field effect transistors in series with each region. Selection signals applied to the selection transistors of an adjacent pair of regions connect one region to the voltage reference and the other region to output to provide an output signal as a function of data stored at a particular addressed storage location.
Inventors
- 👤 R Polkinghorn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:58
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
139 words
A high density read-only memory comprising, a plurality of conducting regions in a semiconductor substrate, a plurality of address lines and a plurality of select lines forming a matrix with said conducting regions, said matrix being associated with bit positions of the memory, alternate ones of said conducting regions being connected to a reference potential and the remaining conducting regions being connected to a common output for said bit positions, a first group of field effect transistors actuated by signals on said address lines, said first group of field effect transistors being selectively connected between adjacent conducting regions for storing data at associated bit positions of the read-only memory, and a second group of field effect transistors actuated by signals on said select lines for selecting conducting regions to be connected to said output and to said reference potential.
Claim 2
Dependent Claim
139 words
A high density read-only memory comprising, a plurality of conducting regions in a semiconductor substrate, a plurality of address lines and a plurality of select lines forming a matrix with said conducting regions, said matrix being associated with bit positions of the memory, alternate ones of said conducting regions being connected to a reference potential and the remaining conducting regions being connected to a common output for said bit positions, a first group of field effect transistors actuated by signals on said address lines, said first group of field effect transistors being selectively connected between adjacent conducting regions for storing data at associated bit positions of the read-only memory, and a second group of field effect transistors actuated by signals on said select lines for selecting conducting regions to be connected to said output and to said reference potential.
Claim 3
Dependent Claim
99 words
The read-only memory recited in claim 1 wherein said second group of field effect transistors are connected in electrical series with said plurality of conducting regions, and means enabling said second group of field effect transistors to remain actuated for a memory address cycle with signals on adjacent ones of said select lines being on during the memory cycle for actuating field effect transistors of said second group in series with adjacent semiconductoR regions during the memory cycle whereby one conducting region is connected to said reference potential while the adjacent conducting region is connected to said common output.
Claim 4
Dependent Claim
124 words
The read-only memory recited in claim 2 further including a third group of field effect transistors connected in electrical series with each of said plurality of conducting regions for precharging said conducting regions to a first voltage level prior to said memory address cycle, and signals on said address lines and said select lines actuating selected ones of said first and second groups of field effect transistors for enabling the charge on the conducting regions corresponding to the signals on said select lines to be provided to the output or to be discharged to said reference potential as a function of the presence or absence of a field effect transistor of said first group of field effect transistors between the adjacent semiconductor regions selected.
Claim 5
Dependent Claim
38 words
The read-only memory recited in claim 3 further including a plurality of said matrixes, said first, said second, and said third groups of field effect transistors for implementing a read-only memory having a plurality of multi-bit memory sections.
Claim 6
Dependent Claim
44 words
The read-only memory recited in claim 3 further including a field effect transistor connected in electrical series with certain ones of said second group of field effect transistors for preventing discharge of non-selected conducting regions to said reference potential during a memory address cycle.
Claim 7
Dependent Claim
117 words
The read-only memory recited in claim 1 wherein the presence of a field effect transistor from said first group of field effect transistors at location between adjacent conducting regions indicates the storage of one state of data and the absence of a field effect transistor at said location indicates the storage of a different logic state of data, the presence of a field effect transistor at said location between adjacent semiconductor regions enabling said adjacent regions to be series-connected between said reference potential and said output if said field effect transistor at said location is actuated by a signal on said address line and if the adjacent conducting regions are selected by signals on said select lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-16 | 1976-10-16 | 1977-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-16 | 1980-10-16 | 1981-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-16 | 1984-10-16 | 1985-04-17 | $7700.00 | Window Closed / Lapsed |