Data decompression apparatus and method

Claim 2

Data buffering and decoding apparatus comprising: data storage means; decoding memory means; write address means for writing data into a selected address of said data storage means; read address means for causing the reading of data from corresponding selected addresses of said data storage means and said decoding memory means; comparison means for comparing data read from the corresponding addresses of said data storage means for said decoding memory means and for producing decoded data from said comparison; and means for writing said decoded data into said decoding memory means at said selected address.

Claim 3

Data buffering and decoding apparatus comprising: data storage means; decoding memory means; write address means for writing data into a selected address of said data storage means; read address means for causing the reading of multiple-line data from corresponding selected addresses of said data storage means and said decoding memory means; latch means for retaining said multiple line data read from the data storage means; line counter means for selecting data of a given line of the data read from the data storage means and latched in said latch means; comparison means for comparing selected line data which is read from the data storage means and received on a first input of said comparison means with data which is read from the corresponding address of the decoding memory means and received on a second input of said comparison means, and for producing decoded data from said comparison; data selection means controlled by said line counter means for selecting data from said latch means and applying it to said first input of said comparison means; output means; and means for providing said decoded data to said output means and for writing said decoded data into said decoding memory means at said selected address.

Claim 4

Data buffering and decoding apparatus comprising: data storage means; decoding memory means; write address means for writing data into a selected address of said data storage means; read address means for causing the reading of multiple-line data from corresponding selected addresses of said data storage means and said decoding memory means; latch means for retaining said multiple line data read from the data storage means; line counter means for selecting data of a given line of the data read from the data storage means and latched in said latch means; comparison means for comparing selected line data which is read from the data storage means and received on a first input of said comparison means with data which is read from the corresponding address of the decoding memory means and received on a second input of said comparison means, and for producing decoded data from said comparison; data selection means controlled by said line counter means for selecting data from said latch means and applying it to said first input of said comparison means; output means; and means for providing said decoded data to said output means and for writing said decoded data into said decoding memory means at said selected address.

Claim 5

The apparatus of claim 2, also including address latch means for latching the address applied to said decoding memory means.

Claim 6

The apparatus of claim 2, also including data latch means for latching the decoded data from the comparison means.

Claim 7

The apparatus of claim 2, also including selection means for selecting a read operation or a write operation; and routing means controlled by said selection means for coupling either said write address means or said read address means to said data storage means.

Claim 8

Data buffering and decoding apparatus comprising: data storage means including a plurality of multi-column storage addresses, the total number of addresses being divisible into a plurality of groups; decoding memory means including a plurality of single-column storage addresses divisible into a plurality of groups, said addresses and groups corresponding to those of the data storage means; write address means for causing the writing of data into the storage means by sequentially addressing multi-column address locations, group by group; read address means for causing the reading of data from corresponding selected multi-column addresses of said data storage means and single column addresses of said decoding memory means, group by group; latch means coupled to said data storage means for latching said multiple column data read from each address of the data storage means; data selection means coupled to said latch means for selecting column data from said latch means; column counting means coupled to said data selection means and sequentially operable for causing said data selection means to select columns of data within a group being read from the data storage means, and causing data for a particular column for all the addresses of a group to be selected before shifting to the next column; comparison means coupled to said data selection means and to said decoding memory means for comparing column data selected by the data selection means with data read from the corresponding address of the decoding memory means, and for producing decoded data from said comparison; output register means; and means for providing said decoded data to said output register means and for writing said decoded data into said decoding memory means at said corresponding address.

Claim 9

Data buffering and decoding apparatus comprising: data storage means including a plurality of multi-column storage addresses, the total number of addresses being divisible into a plurality of groups; decoding memory means including a plurality of single-column storage addresses divisible into a plurality of groups, said addresses and groups corresponding to those of the data storage means; write address means for causing the writing of data into the storage means by sequentially addressing multi-column address locations, group by group; read address means for causing the reading of data from corresponding selected multi-column addresses of said data storage means and single column addresses of said decoding memory means, group by group; latch means coupled to said data storage means for latching said multiple column data read from each address of the data storage means; data selection means coupled to said latch means for selecting column data from said latch means; column counting means coupled to said data selection means and sequentially operable for causing said data selection means to select columns of data within a group being read from the data storage means, and causing data for a particular column for all the addresses of a group to be selected before shifting to the next column; comparison means coupled to said data selection means and to said decoding memory means for comparing column data selected by the data selection means with data read from the corresponding address of the decoding memory means, and for producing decoded data from said comparison; output register means; and means for providing said decoded data to said output register means and for writing said decoded data into said decoding memory means at said corresponding address.

Claim 10

The apparatus of claim 6 in which said data storage means is divided into a plurality of sections of equal numbers of groups, each section including at least one group.

Claim 11

The apparatus of claim 7, in which certain adjacent sections may be made available for the writing of information therein, while other adjacent sections are available for the reading of information therefrom.

Claim 12

The apparatus of claim 7, also including bi-directional counting means for maintaining an indication of whether a given section is fully loaded, partially loaded, or empty, and for controlling reading and writing operations in accordance with the state of said section.