Address translator

Claim 1

A device for translating a first address field including a preselected number of bits A representative of a first address map having X m by Y n address locations into a second address field including a predetermined number of bits B, representative of a second address map having X p by Y q address locations, wherein (1) m is an integer varying from 0 to M, (2) n is an integer varying from 0 to N, (3) p is an integer varying from 0 to P, (4) q is an integer varying from 0 to Q, (5) the value of M is equal to a value of 2 a +b and the value of N is equal to 2 d +e, and (6) d the value of P=2 a +b-c=2 g , and the value of Q=2 d +e+f=2 h , (7) a, b, c, d, e, f, g and h are each whole integers, and (8) said first address field includes at least one bit for indicating when said first address field represents addresses of said first address map where m is greater than 2 a +b-c, said device comprising: (a) sensing means for sensing said at least one bit of said first address field representative of addresses of said first address map where m is equal to or greater than 2 a +b-c; and (b) means responsive to said sensing means for generating the bits of at least a portion of said second address field such that (i) when m is less than 2 a +b-c, said second address field represents the same address locations of said second address map as said first address map; and (ii) when m is equal to or greater than 2 a +b-c, said second address field represents unique address locations of that portion of said second address map where q exceeds 2 d +e respectively corresponding to address locations of that porton of said first address map where m equals or exceeds 2 a +b-c.

Claim 2

A device for translating a first address field including a preselected number of bits A representative of a first address map having X m by Y n address locations into a second address field including a predetermined number of bits B, representative of a second address map having X p by Y q address locations, wherein (1) m is an integer varying from 0 to M, (2) n is an integer varying from 0 to N, (3) p is an integer varying from 0 to P, (4) q is an integer varying from 0 to Q, (5) the value of M is equal to a value of 2 a +b and the value of N is equal to 2 d +e, and (6) d the value of P=2 a +b-c=2 g , and the value of Q=2 d +e+f=2 h , (7) a, b, c, d, e, f, g and h are each whole integers, and (8) said first address field includes at least one bit for indicating when said first address field represents addresses of said first address map where m is greater than 2 a +b-c, said device comprising: (a) sensing means for sensing said at least one bit of said first address field representative of addresses of said first address map where m is equal to or greater than 2 a +b-c; and (b) means responsive to said sensing means for generating the bits of at least a portion of said second address field such that (i) when m is less than 2 a +b-c, said second address field represents the same address locations of said second address map as said first address map; and (ii) when m is equal to or greater than 2 a +b-c, said second address field represents unique address locations of that portion of said second address map where q exceeds 2 d +e respectively corresponding to address locations of that porton of said first address map where m equals or exceeds 2 a +b-c.

Claim 9

A device for translating a first address signal including a first address field representative of the address locations of a pixel map, into a second address signal including a second address field representative of the address locations of a storage map, wherein said pixel map and address map have corresponding address locations which are in the same relative positions, said pixel map includes address locations which do not directly correspond to locations in the storage map, and said storage map includes address locations which do not directly correspond to locations in the pixel map, said device comprising: means for generating said second address signal in response to said first address signal, said means for generating said second address signal including (1) means for transmitting said first address signal as said second address signal when said first address field represents one of said address locations which correspond to address locations of said storage map; and (2) means for transmitting said second address signal as a modification of said first address signal when said first address field represents address locations of said pixel map which do not correspond to locations in said storage map so as to convert each said first address field to said second address field such that the second address field of each such second signal corresponds to a unique address location of said storage map which does not directly correpond to an address location of said pixel map.

Claim 10

A device for translating a first address signal including a first address field representative of the address locations of a pixel map, into a second address signal including a second address field representative of the address locations of a storage map, wherein said pixel map and address map have corresponding address locations which are in the same relative positions, said pixel map includes address locations which do not directly correspond to locations in the storage map, and said storage map includes address locations which do not directly correspond to locations in the pixel map, said device comprising: means for generating said second address signal in response to said first address signal, said means for generating said second address signal including (1) means for transmitting said first address signal as said second address signal when said first address field represents one of said address locations which correspond to address locations of said storage map; and (2) means for transmitting said second address signal as a modification of said first address signal when said first address field represents address locations of said pixel map which do not correspond to locations in said storage map so as to convert each said first address field to said second address field such that the second address field of each such second signal corresponds to a unique address location of said storage map which does not directly correpond to an address location of said pixel map.