US4677594A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Addressing circuit for a matrix display incorporating shift registers formed from static memories and addressing process using such a circuit
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1985-01-30
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Granted: 1987-06-30
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Expires: 2005-01-30
Abstract
Abstract Addressing circuit for a matrix display having shift registers formed by static memories and process for addressing with such a circuit. For a display with p columns, the circuit comprises p register points formed by static memories (M i ), a first series of switches (C 1 ) placed in front of the register points M k-1 , k being an even number between 1 and p, a second series of switches (C 2 ) placed in front of the register points M k and a transfer clock (13) producing a first signal (φ 1 ) controlling the first series of switches, in order to ensure the loading of a "1" signal into the register point (M 1 ) and the transfer of the content of register point M k to register point M k+1 , and a second signal (φ 2 ) controlling the second series of switches for ensuring the transfer of the content of register point M k-1 to register point M k .
Inventors
- 👤 Sylvette Bisotto
- 👤 Jean-Philippe Blanc
- 👤 Bernard Bodin
- 👤 Robert Poujois
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:00
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3685; G09G3/3688; G09G3/3674; G09G3/3681; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/188; G09G3/2007; G09G3/2011
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
240 words
An addressing circuit of p rows or column of elementary display points of a matrix display having p series writing-parallel reading row or column shift register points, switches interposed between the row or column register points, a first transfer clock supplying clock signals controlling the switches for ensuring the movement of information from one register point to the other, characterized in that the first transfer clock produces a first clock signal controlling a first series of switches, one switch of said first series being placed in front of one register point M k-1 , in which k is a number which can assume all the even values between 1 and p, said first clock signal ensuring the loading of a "1" signal into the first register point (M 1 , M' 1 ) and the transfer of the content of register point M k to register point M k+1 , in that the first transfer clock produces a second clock signal of the same frequency as the first clock signal and phase-displaced with respect thereto, controlling a second series of switches, one switch of said second series being placed in front of the register point M k , said second clock signal ensuring the transfer of the content of register point M k-1 to register point M k and in that each register point M k is formed by a single static memory point (M i , N' j ).
Claim 2
Dependent Claim
240 words
An addressing circuit of p rows or column of elementary display points of a matrix display having p series writing-parallel reading row or column shift register points, switches interposed between the row or column register points, a first transfer clock supplying clock signals controlling the switches for ensuring the movement of information from one register point to the other, characterized in that the first transfer clock produces a first clock signal controlling a first series of switches, one switch of said first series being placed in front of one register point M k-1 , in which k is a number which can assume all the even values between 1 and p, said first clock signal ensuring the loading of a "1" signal into the first register point (M 1 , M' 1 ) and the transfer of the content of register point M k to register point M k+1 , in that the first transfer clock produces a second clock signal of the same frequency as the first clock signal and phase-displaced with respect thereto, controlling a second series of switches, one switch of said second series being placed in front of the register point M k , said second clock signal ensuring the transfer of the content of register point M k-1 to register point M k and in that each register point M k is formed by a single static memory point (M i , N' j ).
Claim 3
Dependent Claim
133 words
The addressing circuit according to claim 1, of the p rows of elementary display points of the display, characterized in that said addressing circuit further comprises third and fourth series of switches used for the transfer of a sampled video signal into the elementary display points of one of the p rows, the switches of the third series being located at the output of the registers M k-1 and the switches of the fourth series being located at the output of the registers M k , and in that said addressing circuit comprises a second transfer clock producing a third clock signal controlling the third series of switches and a fourth clock signal of the same frequency as the third clock signal and phase-displaced with respect thereto controlling the fourth series of switches.
Claim 4
Dependent Claim
151 words
A process for addressing p rows or p columns of elementary display points of a matrix display using the addressing circuit according to claim 1, characterized in that the following stages are performed: loading a "1" signal into the first register point (M 1 , M' 1 ) with the aid of the first clock signal, the other register point containing a "0" signal; stepwise transfer of this "1" signal from a register point M k-1 to a register point M k with the aid of the second clock signal, said signal "1" being available at the output of point M k-1 , then from a register point M k to a register point M k+1 with the aid of the first clock signal, the "1" signal being available at the output of point M k , the register points other than M k and M k+1 containing a "0" signal.
Claim 5
Dependent Claim
163 words
The process according to claim 3 for addressing two successive rows of elementary display points of the display, characterized in that the following steps are performed: storing a first video signal in the analog memories having to be transferred to the (k-1)-th row of the display; transfer of said first video signal from the analog memories to the (k-1)-th row with the aid of a third clock signal controlling a switch of a third series of switches connected to the output of the register point M k-1 ; storing a second video signal in the analog memories to be transferred to the k-th row of the display; and transfer of said second video signal from the analog memories to the k-th row with the aid of a fourth clock signal of the same frequency as the third clock signal and phase-displaced relative thereto, controlling a switch of the fourth series of switches connected to the output of the register point M k .
References Cited (Backward Citations)
US4393482A
Cited
US4330852A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-29 | 1990-12-29 | 1991-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-29 | 1994-12-29 | 1995-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-29 | 1998-12-29 | 1999-06-30 | $7700.00 | Window Closed / Lapsed |