Patent US5834956A successfully refreshed from Google Patents.
US5834956A
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Core clock correction in a 2/N mode clocking scheme
Assignee: Intel Corp
•
Filing: 1996-09-06
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Granted: 1998-11-10
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Expires: 2016-09-06
Abstract
Abstract A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
Inventors
- 👤 Chakrapani Pathikonda
- 👤 Matthew A. Fisch
- 👤 Javed S. Barkatullah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:41
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
130 words
A clock generator fabricated on an integrated circuit comprising: a core clock generator to generate a core clock signal; a bus enable generation logic d to generate first and second bus clock enable indications; a first circuitry to generate a bus clock signal by selecting every N/2 cycles of the core clock signal in response to the first and second bus clock enable indications, wherein N is an odd integer greater than two; a detector to determine whether the core clock signal is out of phase with the bus clock signal; and a correction circuitry coupled to the detector to place the core clock signal in phase with the bus clock signal if the detector determines that the core clock signal is out of phase with the bus clock signal.
Claim 2
Dependent Claim
130 words
A clock generator fabricated on an integrated circuit comprising: a core clock generator to generate a core clock signal; a bus enable generation logic d to generate first and second bus clock enable indications; a first circuitry to generate a bus clock signal by selecting every N/2 cycles of the core clock signal in response to the first and second bus clock enable indications, wherein N is an odd integer greater than two; a detector to determine whether the core clock signal is out of phase with the bus clock signal; and a correction circuitry coupled to the detector to place the core clock signal in phase with the bus clock signal if the detector determines that the core clock signal is out of phase with the bus clock signal.
Claim 3
Dependent Claim
21 words
The clock generator defined in claim 1 wherein the detector samples the core clock signal upon deassertion of a reset signal.
Claim 4
Dependent Claim
34 words
The clock generator defined in claim 1 wherein the correction circuitry shifts the core clock signal one phase to place the core clock signal and the bus clock signal in phase with each other.
Claim 5
Dependent Claim
49 words
The clock generator defined in claim 3 wherein the core clock generator comprises a phased-locked loop (PLL) coupled to a divide-by-two counter and provides a frequency clock to the divide-by-two counter, and wherein the correction circuitry swallows one cycle of the frequency clock to shift the core clock signal.
Claim 6
Dependent Claim
33 words
The clock generator defined in claim 4 wherein the phase and frequency of the bus clock signal remains unchanged when the core clock signal is placed in phase with the bus clock signal.
Claim 7
Dependent Claim
30 words
The clock generator defined in claim 5 wherein the core clock signal is shifted 180 degrees if the core clock signal and the bus clock signal are out of phase.
Claim 8
Dependent Claim
112 words
A clock generator fabricated on an integrated circuit comprising: means for generating a core clock signal; means for generating first and second bus clock enable indications; means for generating a bus clock signal by selecting every N/2 cycles of the core clock signal in response to the first and second bus clock enable indications, wherein N is an odd integer greater than two; means for determining whether the core clock signal is out of phase with the bus clock signal; and means for placing the core clock signal in phase with the bus clock signal if the core clock signal is determined to be out of phase with the bus clock signal.
Claim 9
Dependent Claim
112 words
A clock generator fabricated on an integrated circuit comprising: means for generating a core clock signal; means for generating first and second bus clock enable indications; means for generating a bus clock signal by selecting every N/2 cycles of the core clock signal in response to the first and second bus clock enable indications, wherein N is an odd integer greater than two; means for determining whether the core clock signal is out of phase with the bus clock signal; and means for placing the core clock signal in phase with the bus clock signal if the core clock signal is determined to be out of phase with the bus clock signal.
Claim 10
Dependent Claim
55 words
The clock generator defined in claim 7 wherein the means for generating the core clock comprises divide-by-two counter; and a phased-locked loop (PLL) coupled to the divide-by-two counter to provides a frequency clock to the divide-by-two counter, and wherein the correction circuitry swallows one cycle of the frequency clock to shift the core clock signal.
Claim 11
Dependent Claim
23 words
The clock generator defined in claim 7 wherein the means for determining samples the core clock signal upon deassertion of a reset signal.
Claim 12
Dependent Claim
44 words
The clock generator defined in claim 7 means for placing the core clock signal in phase with the bus clock signal shifts the core clock signal one phase to place the core clock signal and the bus clock signal in phase with each other.
Claim 13
Dependent Claim
33 words
The clock generator defined in claim 8 wherein the phase and frequency of the bus clock signal remains unchanged when the core clock signal is placed in phase with the bus clock signal.
Claim 14
Dependent Claim
30 words
The clock generator defined in claim 11 wherein the core clock signal is shifted 180 degrees if the core clock signal and the bus clock signal are out of phase.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |