Apparatus for operating a microprocessor core and bus controller at a speed greater than the speed of a bus clock speed

Claim 2

A microprocessor formed in a single integrated circuit chip for use in a computer system having a bus transferring data throughout the computer system including the microprocessor, wherein said microprocessor is clocked by an external clock signal, said microprocessor comprising: clock generation means for generating a plurality of clock signals in response to said external clock signal, said clock generation means including means for generating at least one core clock signal at a first frequency and means for generating at least one bus clock signal at a second frequency that is slower than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core operates at the clock speed of said at least one core clock signal; and bus controller means coupled to the clock generation means, the CPU core and the bus for transferring data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core and the bus controller means operates at the clock speed of said at least one core clock signal.

Claim 3

The microprocessor defined by claim 1 wherein said first frequency is an integer multiple of said second frequency.

Claim 4

The microprocessor defined in claim 1 wherein the CPU core includes a processing unit executing instructions, an instruction-storage storing instructions, and a transfer means coupled to said processing unit and said instruction-storage for transferring instructions from the instruction-storage to the processing unit.

Claim 5

The microprocessor defined by claim 3 wherein said integer multiple is two, such that said first frequency of said at least one core clock signal is twice said second frequency of said at least one bus clock signal.

Claim 6

A microprocessor formed in a single integrated circuit chip for use in a computer system having a bus for transferring data throughout the computer system including the microprocessor, wherein said microprocessor is clocked by an external clock signal at a first frequency, said microprocessor comprising: clock generation means for generating at least one core clock signal and at least one bus clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency and being an integer multiple of said first frequency, wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, wherein said clock generation means comprises core clock signal generation means for generating said at least one core clock signal in response to said external clock signal; and bus clock signal generation means coupled to said core clock signal generation means, said bus clock signal generation means for receiving at least one of said at least one core clock signal and generating said at least one bus clock signal in response to said at least one core clock signal, wherein said bus clock signal generation means masks said at least one core clock signal to generate said at least one bus clock signal while said at least one core clock signal remains unaffected; a CPU core coupled to the clock generation means and responsive to said at least one core clock signal, wherein the CPU core includes a CPU for executing instructions, an instruction-storage means for storing instructions, and a transfer means coupled to said CPU and said instruction-storage means for transferring instructions from the instruction-storage means to the CPU, wherein said core CPU operates at the clock speed of said at least one core clock signal; and bus controller means coupled to the clock generation means, the CPU core and the bus and responsive to said at least one bus clock signal for transferring data between said CPU core and said bus while said CPU core operates at the clock speed of said at least one core clock signal.

Claim 7

A microprocessor formed in a single integrated circuit chip for use in a computer system having a bus for transferring data throughout the computer system including the microprocessor, wherein said microprocessor is clocked by an external clock signal at a first frequency, said microprocessor comprising: clock generation means for generating at least one core clock signal and at least one bus clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency and being an integer multiple of said first frequency, wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, wherein said clock generation means comprises core clock signal generation means for generating said at least one core clock signal in response to said external clock signal; and bus clock signal generation means coupled to said core clock signal generation means, said bus clock signal generation means for receiving at least one of said at least one core clock signal and generating said at least one bus clock signal in response to said at least one core clock signal, wherein said bus clock signal generation means masks said at least one core clock signal to generate said at least one bus clock signal while said at least one core clock signal remains unaffected; a CPU core coupled to the clock generation means and responsive to said at least one core clock signal, wherein the CPU core includes a CPU for executing instructions, an instruction-storage means for storing instructions, and a transfer means coupled to said CPU and said instruction-storage means for transferring instructions from the instruction-storage means to the CPU, wherein said core CPU operates at the clock speed of said at least one core clock signal; and bus controller means coupled to the clock generation means, the CPU core and the bus and responsive to said at least one bus clock signal for transferring data between said CPU core and said bus while said CPU core operates at the clock speed of said at least one core clock signal.

Claim 8

The microprocessor defined by claim 5 wherein said second frequency is twice the first frequency.

Claim 9

The microprocessor defined by claim 5 wherein said clock generation means comprises a phase locked loop.

Claim 10

The microprocessor defined by claim 7 wherein said core clock generation means comprises a phased lock loop including: a phase detector means for receiving said external clock signal and a feedback signal and for generating a first signal in response thereto that is a measure of the phase difference between said external clock signal and said feedback signal; a voltage generation means for generating a voltage control signal in accordance with said first signal; a voltage-controlled oscillator means for generating at least one core clock signal in response to said voltage control signal, the frequency of said at least one core clock signal varying in accordance with the level of said feedback voltage; and a frequency divider means for generating said feedback signal in response to said at least one core clock signal, said feedback signal having a frequency which is a multiple of said at least one core clock signal, such that said oscillator produces a signal which is N times the frequency of said external clock signal.

Claim 11

The microprocessor defined by claim 8 wherein said frequency divider comprises: first logic means for generating a masking signal in response to at least one of said at least one core clock signal, said masking signal being at a first state or a second state; and second logic means for generating said feedback signal in response to said one or core clock signal and said masking signal, such that said second logic means generates said feedback signal when said masking signal is in said first state and masks said feedback signal when said masking signal is in said second state.

Claim 12

The microprocessor defined by claim 8 wherein said frequency divider generates said at least one bus clock signal.

Claim 13

A microprocessor for use in a computer system that includes an address bus and a data bus for transferring address information and data information respectively, wherein said microprocessor being clocked by an external global clock signal, said microprocessor comprising: a CPU core that executes a plurality of instructions in response to at least one core clock signal; a bus controller unit coupled to the CPU core, said bus controller unit transferring information between the CPU core and the address bus and data bus in response to at least one bus clock signal; a circuit coupled to the CPU core and the bus controller unit for allowing the CPU core to be clocked at N times the frequency at which address information and data information is transferred on the address bus and data bus respectively, said circuit including a phase detector means for detecting the phase difference between said external global clock and a feedback signal, said phase detector means including means for receiving said external clock signal and said feedback signal and means for determining the phase difference between said external clock signal and said feedback signal, wherein the phase detector includes a means for generating a first signal that represents the measure of the phase difference between said external clock signal and said feedback signal; a voltage generation means coupled to said phase detector means for generating a voltage control signal in response to said first signal; a voltage-controlled oscillator means coupled to said voltage generation means for generating said at least one core clock signal in response to said voltage control signal, the frequency of said at least one core clock signal varying in accordance with the voltage level of said voltage control signal; first logic means coupled to at least one of said at least one core clock signal for generating a masking signal in response to said at least one of said at least one core clock signal, said masking signal being at a first state or a second state; and second logic means coupled to said voltage-controlled oscillator means and said first logic means for generating said at least one bus clock signal in response to said one core clock signal and said masking signal, such that said second logic means generates said at least one bus clock signal when said masking signal is in said first state and masks said at least one bus clock signal when said masking signal is in said second state, said at least one core clock signal having a frequency which is a multiple of the frequency of said at least one bus clock signal, wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, and further wherein one of said at least one bus clock signal being said feedback signal, such that said oscillator produces said at least one core clock signal which are N times the frequency of said external clock signal; and wherein the bus control unit transfers information between said CPU core and said address bus and data bus at the clock speed of said at least one bus clock signal while said CPU core operates at the clock speed of said at least one core clock signal; and further wherein the CPU core, the bus controller unit and the circuit are formed in a single integrated circuit.

Claim 14

A microprocessor for use in a computer system that includes an address bus and a data bus for transferring address information and data information respectively, wherein said microprocessor being clocked by an external global clock signal, said microprocessor comprising: a CPU core that executes a plurality of instructions in response to at least one core clock signal; a bus controller unit coupled to the CPU core, said bus controller unit transferring information between the CPU core and the address bus and data bus in response to at least one bus clock signal; a circuit coupled to the CPU core and the bus controller unit for allowing the CPU core to be clocked at N times the frequency at which address information and data information is transferred on the address bus and data bus respectively, said circuit including a phase detector means for detecting the phase difference between said external global clock and a feedback signal, said phase detector means including means for receiving said external clock signal and said feedback signal and means for determining the phase difference between said external clock signal and said feedback signal, wherein the phase detector includes a means for generating a first signal that represents the measure of the phase difference between said external clock signal and said feedback signal; a voltage generation means coupled to said phase detector means for generating a voltage control signal in response to said first signal; a voltage-controlled oscillator means coupled to said voltage generation means for generating said at least one core clock signal in response to said voltage control signal, the frequency of said at least one core clock signal varying in accordance with the voltage level of said voltage control signal; first logic means coupled to at least one of said at least one core clock signal for generating a masking signal in response to said at least one of said at least one core clock signal, said masking signal being at a first state or a second state; and second logic means coupled to said voltage-controlled oscillator means and said first logic means for generating said at least one bus clock signal in response to said one core clock signal and said masking signal, such that said second logic means generates said at least one bus clock signal when said masking signal is in said first state and masks said at least one bus clock signal when said masking signal is in said second state, said at least one core clock signal having a frequency which is a multiple of the frequency of said at least one bus clock signal, wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, and further wherein one of said at least one bus clock signal being said feedback signal, such that said oscillator produces said at least one core clock signal which are N times the frequency of said external clock signal; and wherein the bus control unit transfers information between said CPU core and said address bus and data bus at the clock speed of said at least one bus clock signal while said CPU core operates at the clock speed of said at least one core clock signal; and further wherein the CPU core, the bus controller unit and the circuit are formed in a single integrated circuit.

Claim 15

The microprocessor defined by claim 11 wherein said second logic means generates said masking signal that masks said bus clock signal every other signal, such that said feedback signal drives said oscillator to produce said at least one core clock signal which are two times the frequency of said external clock signal.

Claim 16

A microprocessor formed in a single integrated circuit chip for use in a computer system having a bus transferring data throughout the computer system including the microprocessor, wherein said microprocessor is clocked by an external clock signal at a first frequency, said microprocessor comprising: a CPU core responsive to a core clock signal, said CPU core including a CPU executing instructions, an instruction-storage means for storing instructions, and a transfer means coupled to said CPU and said instruction-storage means for transferring instructions from the instruction-storage means to the CPU; and bus controller means coupled to said CPU core and said bus for transferring data between said CPU core and said bus, wherein said CPU core and the bus controller means operate at a faster frequency than said bus and said external clock, and further wherein the bus is clocked with a bus clock signal having a pulse width equal to the pulse width of the core clock signal clocking the CPU core, wherein the bus controller means transfers data between said CPU core and said bus at the clock speed of said bus clock signal, while said CPU core and the bus controller means operate at the clock speed of said core clock signal.

Claim 17

A microprocessor formed in a single integrated circuit chip for use in a computer system having a bus transferring data throughout the computer system including the microprocessor, wherein said microprocessor is clocked by an external clock signal at a first frequency, said microprocessor comprising: a CPU core responsive to a core clock signal, said CPU core including a CPU executing instructions, an instruction-storage means for storing instructions, and a transfer means coupled to said CPU and said instruction-storage means for transferring instructions from the instruction-storage means to the CPU; and bus controller means coupled to said CPU core and said bus for transferring data between said CPU core and said bus, wherein said CPU core and the bus controller means operate at a faster frequency than said bus and said external clock, and further wherein the bus is clocked with a bus clock signal having a pulse width equal to the pulse width of the core clock signal clocking the CPU core, wherein the bus controller means transfers data between said CPU core and said bus at the clock speed of said bus clock signal, while said CPU core and the bus controller means operate at the clock speed of said core clock signal.

Claim 18

The microprocessor as defined in claim 13 wherein the bus clock signal is a quarter duty cycle clock signal.

Claim 19

A microprocessor formed in a single integrated circuit chip for use in a computer system having a bus for transferring data throughout the computer system including the microprocessor, wherein said microprocessor is clocked by an external clock signal, said microprocessor comprising: cache memory means for storing data and instructions, wherein the cache memory means includes a transfer means for transferring instructions from the cache memory means; instruction decoder means coupled to the cache memory means for receiving and interpreting instructions to determine the operation of each of said instructions, such that each of said instructions is decoded; logic means coupled to said instructions decoder means and said cache memory means for performing the operation of said decoded instructions, wherein said logic means performs each of the operations using data from said cache memory means when indicated by the operations of the decoded instructions, such that the instructions are executed; bus controller means coupled to said cache memory means, instruction decoder means and said logic means for transferring data between the bus and said cache memory means, instruction decoder and said logic means; and clock generation means coupled to said bus controller means, cache memory means, instruction decoder means, and said logic means, said clock generation means for generating a plurality of clock signals in response to said external clock signal, said clock generation means including means for generating at least one first clock signal at a first frequency and means for generating at least one second clock signal at a second frequency, and further wherein the width of each pulse of said at least one second clock signal equals the width of each pulse of said at least one first clock signal, wherein said clock generation means clocks said cache memory means, instruction decoder means, and the bus controller means and said logic means with said at least one first clock signal and clocks the transfer of data by said bus controller means with said at least one second clock signal, wherein the bus controller means transfers data between the bus and said cache memory means, instruction decoder means and said logic means at the second frequency, while said cache memory means, instruction decoder means, the bus controller means and said logic means operate at the first frequency.

Claim 20

A microprocessor formed in a single integrated circuit chip for use in a computer system having a bus for transferring data throughout the computer system including the microprocessor, wherein said microprocessor is clocked by an external clock signal, said microprocessor comprising: cache memory means for storing data and instructions, wherein the cache memory means includes a transfer means for transferring instructions from the cache memory means; instruction decoder means coupled to the cache memory means for receiving and interpreting instructions to determine the operation of each of said instructions, such that each of said instructions is decoded; logic means coupled to said instructions decoder means and said cache memory means for performing the operation of said decoded instructions, wherein said logic means performs each of the operations using data from said cache memory means when indicated by the operations of the decoded instructions, such that the instructions are executed; bus controller means coupled to said cache memory means, instruction decoder means and said logic means for transferring data between the bus and said cache memory means, instruction decoder and said logic means; and clock generation means coupled to said bus controller means, cache memory means, instruction decoder means, and said logic means, said clock generation means for generating a plurality of clock signals in response to said external clock signal, said clock generation means including means for generating at least one first clock signal at a first frequency and means for generating at least one second clock signal at a second frequency, and further wherein the width of each pulse of said at least one second clock signal equals the width of each pulse of said at least one first clock signal, wherein said clock generation means clocks said cache memory means, instruction decoder means, and the bus controller means and said logic means with said at least one first clock signal and clocks the transfer of data by said bus controller means with said at least one second clock signal, wherein the bus controller means transfers data between the bus and said cache memory means, instruction decoder means and said logic means at the second frequency, while said cache memory means, instruction decoder means, the bus controller means and said logic means operate at the first frequency.

Claim 21

The microprocessor as described in claim 15 wherein said first frequency is an integer multiple of said second frequency.

Claim 22

The microprocessor as described in claim 16 wherein said integer is two, such that the first frequency is twice that of said second frequency.

Claim 23

The microprocessor as described in claim 15 wherein said at least one second clock signal is a quarter duty cycle clock signal.

Claim 24

A computer system comprising: a bus transferring data throughout the computer system, wherein the bus operates at a first frequency; a memory coupled to the bus; a processor formed in a single integrated circuit chip and coupled to the bus, wherein said processor is clocked by an external clock signal, said microprocessor comprising a clock generator that generates at least one core clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said second frequency being faster than said first frequency; a CPU core coupled to the clock generator, wherein the CPU core includes a CPU that executes instructions in response to and at the clock speed of said at least one core clock signal; and a bus controller coupled to the CPU core, the clock generator and the bus, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of at least one bus clock signal while said CPU core and the bus controller operate at the clock speed of said at least one core clock signal, and further wherein the width of each pulse of said at least one core clock signal equals the width of each pulse of said at least one bus clock signal.

Claim 25

A computer system comprising: a bus transferring data throughout the computer system, wherein the bus operates at a first frequency; a memory coupled to the bus; a processor formed in a single integrated circuit chip and coupled to the bus, wherein said processor is clocked by an external clock signal, said microprocessor comprising a clock generator that generates at least one core clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said second frequency being faster than said first frequency; a CPU core coupled to the clock generator, wherein the CPU core includes a CPU that executes instructions in response to and at the clock speed of said at least one core clock signal; and a bus controller coupled to the CPU core, the clock generator and the bus, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of at least one bus clock signal while said CPU core and the bus controller operate at the clock speed of said at least one core clock signal, and further wherein the width of each pulse of said at least one core clock signal equals the width of each pulse of said at least one bus clock signal.

Claim 26

The computer system defined in claim 19 wherein said second frequency is an integer multiple of said first frequency.

Claim 27

The computer system defined in claim 19 wherein said clock generator generates said at least one bus clock signal to clock transfers by the bus controller between the CPU core and the bus.

Claim 28

The computer system defined in claim 19 wherein the clock generator comprises a phase locked loop.

Claim 29

The computer system defined in claim 19 wherein said second frequency is an integer multiple of said first frequency.

Claim 30

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system operating at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising: a clock generator that generates at least one core clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said second frequency being faster than said first frequency; a CPU core coupled to the clock generator, wherein the CPU core includes a CPU that executes instructions in response to and at the clock speed of said at least one core clock signal; and a bus controller coupled to the CPU core, the clock generator, and the bus, wherein the bus controller transfers data between said CPU core and said bus at a clock speed of at least one bus clock signal at the first frequency while said CPU core and the bus controller operate under control of said at least one core clock signal at the second frequency, wherein the width of each pulse of said at least one core clock signal equals the width of each pulse of said at least one bus clock signal.

Claim 31

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system operating at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising: a clock generator that generates at least one core clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said second frequency being faster than said first frequency; a CPU core coupled to the clock generator, wherein the CPU core includes a CPU that executes instructions in response to and at the clock speed of said at least one core clock signal; and a bus controller coupled to the CPU core, the clock generator, and the bus, wherein the bus controller transfers data between said CPU core and said bus at a clock speed of at least one bus clock signal at the first frequency while said CPU core and the bus controller operate under control of said at least one core clock signal at the second frequency, wherein the width of each pulse of said at least one core clock signal equals the width of each pulse of said at least one bus clock signal.

Claim 32

The processor defined in claim 24 wherein said second frequency is an integer multiple of said first frequency.

Claim 33

The processor defined in claim 24 wherein said clock generator generates said at least one bus clock signal to clock transfers by the bus controller between the CPU core and the bus.

Claim 34

The processor defined in claim 24 wherein said clock generator comprises: a core clock signal generator that generates said at least one core clock signal in response to said external clock signal; and a bus clock signal generator coupled to said core clock signal generator, said bus clock signal generator derives said at least one bus clock signal from said at least one core clock signal.

Claim 35

The processor defined in claim 24 wherein the clock generator comprises a phase locked loop.

Claim 36

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system operating at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising: a clock generator that generates at least one core clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said second frequency being faster than said first frequency, wherein said clock generator comprises: a core clock signal generator that generates said at least one core clock signal in response to said external clock signal, and a bus clock signal generator coupled to said core clock signal generator, wherein said bus clock signal generator derives said at least one bus clock signal from said at least one core clock signal by masking a predetermined number of pulses of said at least one core clock signal every N number of pulses, while said at least one core clock signal remains unaffected; a CPU core coupled to the clock generator, wherein the CPU core includes a CPU that executes instructions in response to and at the clock speed of said at least one core clock signal; and a bus controller coupled to the CPU core and the bus, wherein the bus controller transfers data between said CPU core and said bus at a clock speed of at least one bus clock signal at the first frequency while said CPU core operates under control of said at least one core clock signal at the second frequency, wherein the width of each pulse of said at least one core clock signal equals the width of each pulse of said at least one bus clock signal.

Claim 37

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system operating at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising: a clock generator that generates at least one core clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said second frequency being faster than said first frequency, wherein said clock generator comprises: a core clock signal generator that generates said at least one core clock signal in response to said external clock signal, and a bus clock signal generator coupled to said core clock signal generator, wherein said bus clock signal generator derives said at least one bus clock signal from said at least one core clock signal by masking a predetermined number of pulses of said at least one core clock signal every N number of pulses, while said at least one core clock signal remains unaffected; a CPU core coupled to the clock generator, wherein the CPU core includes a CPU that executes instructions in response to and at the clock speed of said at least one core clock signal; and a bus controller coupled to the CPU core and the bus, wherein the bus controller transfers data between said CPU core and said bus at a clock speed of at least one bus clock signal at the first frequency while said CPU core operates under control of said at least one core clock signal at the second frequency, wherein the width of each pulse of said at least one core clock signal equals the width of each pulse of said at least one bus clock signal.

Claim 38

The processor defined in claim 29 wherein the bus clock signal generator masks every other pulse of said at least one core clock signal.

Claim 39

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system operating at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising: a clock generator that generates at least one core clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said second frequency being faster than said first frequency, wherein the clock generator comprises a phase locked loop having a phase detector that detects the phase difference between said external global clock and a feedback signal, said phase detector generates a first signal that represents a measure of the phase difference between said external clock signal and said feedback signal; a voltage generator coupled to said phase detector that generates a voltage control signal in response to said first signal; a voltage-controlled oscillator (VCO) coupled to said voltage generator, wherein the VCO generates said at least one core clock signal in response to said voltage control signal, the frequency of said at least one core clock signal varying in accordance with the voltage level of said voltage control signal; a first logic circuit coupled to at least one of said at least one core clock signal to generates a masking signal in response to said at least one of said at least one core clock signal, said masking signal being at a first state or a second state; and a second logic circuit coupled to said VCO and said first logic circuit to generate said at least one bus clock signal in response to said one core clock signal and said masking signal, such that said second logic circuit generates said at least one bus clock signal when said masking signal is in said first state and masks said at least one bus clock signal when said masking signal is in said second state, said at least one core clock signal having a frequency which is a multiple of the frequency of said at least one bus clock signal, and wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, and further wherein one of said at least one bus clock signal comprises said feedback signal, such that said VCO produces said at least one core clock signal which are N times the frequency of said external clock signal; a CPU core coupled to the clock generator, wherein the CPU core includes a CPU that executes instructions in response to and at the clock speed of said at least one core clock signal; and a bus controller coupled to the CPU core and the bus, wherein the bus controller transfers data between said CPU core and said bus at a clock speed of at least one bus clock signal at the first frequency while said CPU core operates under control of said at least one core clock signal at the second frequency, wherein the width of each pulse of said at least one core clock signal equals the width of each pulse of said at least one bus clock signal.

Claim 40

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system operating at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising: a clock generator that generates at least one core clock signal in response to said external clock signal, said at least one core clock signal being at a second frequency, said second frequency being faster than said first frequency, wherein the clock generator comprises a phase locked loop having a phase detector that detects the phase difference between said external global clock and a feedback signal, said phase detector generates a first signal that represents a measure of the phase difference between said external clock signal and said feedback signal; a voltage generator coupled to said phase detector that generates a voltage control signal in response to said first signal; a voltage-controlled oscillator (VCO) coupled to said voltage generator, wherein the VCO generates said at least one core clock signal in response to said voltage control signal, the frequency of said at least one core clock signal varying in accordance with the voltage level of said voltage control signal; a first logic circuit coupled to at least one of said at least one core clock signal to generates a masking signal in response to said at least one of said at least one core clock signal, said masking signal being at a first state or a second state; and a second logic circuit coupled to said VCO and said first logic circuit to generate said at least one bus clock signal in response to said one core clock signal and said masking signal, such that said second logic circuit generates said at least one bus clock signal when said masking signal is in said first state and masks said at least one bus clock signal when said masking signal is in said second state, said at least one core clock signal having a frequency which is a multiple of the frequency of said at least one bus clock signal, and wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, and further wherein one of said at least one bus clock signal comprises said feedback signal, such that said VCO produces said at least one core clock signal which are N times the frequency of said external clock signal; a CPU core coupled to the clock generator, wherein the CPU core includes a CPU that executes instructions in response to and at the clock speed of said at least one core clock signal; and a bus controller coupled to the CPU core and the bus, wherein the bus controller transfers data between said CPU core and said bus at a clock speed of at least one bus clock signal at the first frequency while said CPU core operates under control of said at least one core clock signal at the second frequency, wherein the width of each pulse of said at least one core clock signal equals the width of each pulse of said at least one bus clock signal.

Claim 41

A computer system comprising: a bus transferring data throughout the computer system, wherein the bus operates at a first frequency; a memory coupled to the bus; a processor formed in a single integrated circuit chip and coupled to the bus, wherein said processor is clocked by an external clock signal, said microprocessor comprising a clock generator that generates at least one core clock signal and at least one bus clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core includes an instruction memory that stores instructions and a CPU executing instructions at the clock speed of said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core and the bus controller operate at the clock speed of said at least one core clock signal.

Claim 42

A computer system comprising: a bus transferring data throughout the computer system, wherein the bus operates at a first frequency; a memory coupled to the bus; a processor formed in a single integrated circuit chip and coupled to the bus, wherein said processor is clocked by an external clock signal, said microprocessor comprising a clock generator that generates at least one core clock signal and at least one bus clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core includes an instruction memory that stores instructions and a CPU executing instructions at the clock speed of said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core and the bus controller operate at the clock speed of said at least one core clock signal.

Claim 43

The computer system defined in claim 32 wherein said at least one bus clock signal comprises a quarter duty cycle signal.

Claim 44

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system that operates at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising a clock generator that generates at least one core clock signal and at least one bus clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core includes an instruction memory that stores instructions and a CPU executing instructions at the clock speed of said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core and the bus controller operate at the clock speed of said at least one core clock signal.

Claim 45

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system that operates at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising a clock generator that generates at least one core clock signal and at least one bus clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core includes an instruction memory that stores instructions and a CPU executing instructions at the clock speed of said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core and the bus controller operate at the clock speed of said at least one core clock signal.

Claim 46

The processor defined in claim 34 wherein said second frequency is an integer multiple of said first frequency.

Claim 47

The processor defined in claim 34 wherein said clock generator generates said at least one bus clock signal to clock transfers by the bus controller between the CPU core and the bus.

Claim 48

The processor defined in claim 34 wherein said clock generator comprises: a core clock signal generator that generates said at least one core clock signal in response to said external clock signal; and a bus clock signal generator coupled to said core clock signal generator, said bus clock signal generator derives said at least one bus clock signal from said at least one core clock signal.

Claim 49

The processor defined in claim 34 wherein the clock generator comprises a phase locked loop.

Claim 50

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system that operates at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising: a clock generator that generates at least one core clock signal and at least one bus clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, wherein said clock generator comprises a core clock signal generator that generates said at least one core clock signal in response to said external clock signal, and a bus clock signal generator coupled to said core clock signal generator, wherein said bus clock signal generator derives said at least one bus clock signal from said at least one core clock signal by masking a predetermined number of pulses of said at least one core clock signal every N number of pulses, while said at least one core clock signal remains unaffected; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core includes an instruction memory that stores instructions and a CPU executing instructions at the clock speed of said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus and responsive to said at least one bus clock signal, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core operates at the clock speed of said at least one core clock signal.

Claim 51

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system that operates at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising: a clock generator that generates at least one core clock signal and at least one bus clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, wherein said clock generator comprises a core clock signal generator that generates said at least one core clock signal in response to said external clock signal, and a bus clock signal generator coupled to said core clock signal generator, wherein said bus clock signal generator derives said at least one bus clock signal from said at least one core clock signal by masking a predetermined number of pulses of said at least one core clock signal every N number of pulses, while said at least one core clock signal remains unaffected; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core includes an instruction memory that stores instructions and a CPU executing instructions at the clock speed of said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus and responsive to said at least one bus clock signal, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core operates at the clock speed of said at least one core clock signal.

Claim 52

The processor defined in claim 39 wherein the bus clock signal generator masks every other pulse of said at least one core clock signal.

Claim 53

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system that operates at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising a clock generator that generates at least one core clock signal and at least one bus clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, wherein the clock generator comprises a phase locked loop having a phase detector that detects the phase difference between said external global clock and a feedback signal, said phase detector generates a first signal that represents a measure of the phase difference between said external clock signal and said feedback signal; a voltage generator coupled to said phase detector that generates a voltage control signal in response to said first signal; a voltage-controlled oscillator (VCO) coupled to said voltage generator, wherein the VCO generates said at least one core clock signal in response to said voltage control signal, the frequency of said at least one core clock signal varying in accordance with the voltage level of said voltage control signal; a first logic circuit coupled to at least one of said at least one core clock signal to generates a masking signal in response to said at least one of said at least one core clock signal, said masking signal being at a first state or a second state; and a second logic circuit coupled to said VCO and said first logic circuit to generate said at least one bus clock signal in response to said one core clock signal and said masking signal, such that said second logic circuit generates said at least one bus clock signal when said masking signal is in said first state and masks said at least one bus clock signal when said masking signal is in said second state, said at least one core clock signal having a frequency which is a multiple of the frequency of said at least one bus clock signal, and wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, and further wherein one of said at least one bus clock signal comprises said feedback signal, such that said VCO produces said at least one core clock signal which are N times the frequency of said external clock signal; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core includes an instruction memory that stores instructions and a CPU executing instructions at the clock speed of said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus and responsive to said at least one bus clock signal, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core operates at the clock speed of said at least one core clock signal.

Claim 54

A processor formed in a single integrated circuit chip and coupled to a bus in a computer system that operates at a first frequency, wherein said processor is clocked by an external clock signal, said microprocessor comprising a clock generator that generates at least one core clock signal and at least one bus clock signal, said at least one core clock signal being at a second frequency, said at least one bus clock signal being at said first frequency, said second frequency being faster than said first frequency, and further wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, wherein the clock generator comprises a phase locked loop having a phase detector that detects the phase difference between said external global clock and a feedback signal, said phase detector generates a first signal that represents a measure of the phase difference between said external clock signal and said feedback signal; a voltage generator coupled to said phase detector that generates a voltage control signal in response to said first signal; a voltage-controlled oscillator (VCO) coupled to said voltage generator, wherein the VCO generates said at least one core clock signal in response to said voltage control signal, the frequency of said at least one core clock signal varying in accordance with the voltage level of said voltage control signal; a first logic circuit coupled to at least one of said at least one core clock signal to generates a masking signal in response to said at least one of said at least one core clock signal, said masking signal being at a first state or a second state; and a second logic circuit coupled to said VCO and said first logic circuit to generate said at least one bus clock signal in response to said one core clock signal and said masking signal, such that said second logic circuit generates said at least one bus clock signal when said masking signal is in said first state and masks said at least one bus clock signal when said masking signal is in said second state, said at least one core clock signal having a frequency which is a multiple of the frequency of said at least one bus clock signal, and wherein the width of each pulse of said at least one bus clock signal equals the width of each pulse of said at least one core clock signal, and further wherein one of said at least one bus clock signal comprises said feedback signal, such that said VCO produces said at least one core clock signal which are N times the frequency of said external clock signal; a CPU core coupled to receive and responsive to said at least one core clock signal, wherein the CPU core includes an instruction memory that stores instructions and a CPU executing instructions at the clock speed of said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus and responsive to said at least one bus clock signal, wherein the bus controller transfers data between said CPU core and said bus at the clock speed of said at least one bus clock signal while said CPU core operates at the clock speed of said at least one core clock signal.