US5325516A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor system with dual clock
Assignee: Intel Corp
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Filing: 1992-03-09
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Granted: 1994-06-28
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Expires: 2012-03-09
Abstract
Abstract The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e. the address status signal) generated by the CPU. The ADS and RDY signals must be modified in a first way if the CPU calls for a memory cycle at the beginning of a bus cycle and in a second way if the CPU calls for a memory cycle in the middle of a CPU cycle. The use of a CPU clock speed doubler in combination with a write-back cache achieves truly synergistic increases in system speed.
Inventors
- 👤 James S. Blomgren
- 👤 Mark Semmelmeyer
- 👤 Tuan Luong
- 👤 Gary Baum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:37
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
165 words
A computer including, memory system operating at a first clock rate, said memory system including a memory bus operating at said first clock rate, an B-ADS control line, activation of which indicates that a memory cycle is desired, and a B-RDY control line, a signal on which indicates that the desired data is on said memory bus, and a single chip microprocessor that includes, a CPU operating at a multiple of said first clock rate, said CPU generating an C-ADS signal when access to memory is desired and said data is not in said cache, and responsive to a C-RDY line to accept data from said memory bus, a memory cache for storing data required by said CPU, and a bus interface unit which includes, means for transforming said B-RDY signal to said C-RDY signal and means for transforming said C-ADS signal into said B-ADS signal, whereby said CPU can operate at a speed which is a multiple of the speed of said memory system.
Claim 2
Dependent Claim
165 words
A computer including, memory system operating at a first clock rate, said memory system including a memory bus operating at said first clock rate, an B-ADS control line, activation of which indicates that a memory cycle is desired, and a B-RDY control line, a signal on which indicates that the desired data is on said memory bus, and a single chip microprocessor that includes, a CPU operating at a multiple of said first clock rate, said CPU generating an C-ADS signal when access to memory is desired and said data is not in said cache, and responsive to a C-RDY line to accept data from said memory bus, a memory cache for storing data required by said CPU, and a bus interface unit which includes, means for transforming said B-RDY signal to said C-RDY signal and means for transforming said C-ADS signal into said B-ADS signal, whereby said CPU can operate at a speed which is a multiple of the speed of said memory system.
Claim 3
Dependent Claim
25 words
The system recited in claim 1 wherein said microprocessor includes a write-back cache, whereby said CPU is not constrained by the capacity of said bus.
Claim 4
Dependent Claim
22 words
The system recited in claim 1 wherein said first clock rate is 33 MHz and said second clock rate is 66 MHz.
Claim 5
Dependent Claim
13 words
The system recited in claim 3 wherein said microprocessor includes a write-back cache.
Claim 6
Dependent Claim
36 words
The system recited in claim 1 wherein said C-ADS signal generated by said CPU is shorted than said B-ADS signal required by said memory system and wherein said B-RDY signal is longer than said C-RDY signal.
Claim 7
Independent Claim
190 words
A system including, a memory system operating at a first speed, said memory system including a memory bus operating at said first speed, said memory system have a plurality of control signal lines including a first control line which is activated when access to memory system is desired and a second control line which indicates that said memory system has provided data on said memory bus, a single chip microprocessor operating at a second speed, said second speed being a multiple of said first speed, said single chip microprocessor having a plurality of memory control signal lines including (1) a control line which is activated to indicate that said CPU desires access to said memory system and (2) a control line which is activated to indicate that said CPU can accept data which is on said bus, and a bus interface unit connecting said single chip microprocessor to said memory system and for modifying said control signals from said memory to conform to the control signal of said single chip microprocessor and for modifying the control signals from said microprocessor to conform to the control signals of said memory system.
Claim 8
Independent Claim
190 words
A system including, a memory system operating at a first speed, said memory system including a memory bus operating at said first speed, said memory system have a plurality of control signal lines including a first control line which is activated when access to memory system is desired and a second control line which indicates that said memory system has provided data on said memory bus, a single chip microprocessor operating at a second speed, said second speed being a multiple of said first speed, said single chip microprocessor having a plurality of memory control signal lines including (1) a control line which is activated to indicate that said CPU desires access to said memory system and (2) a control line which is activated to indicate that said CPU can accept data which is on said bus, and a bus interface unit connecting said single chip microprocessor to said memory system and for modifying said control signals from said memory to conform to the control signal of said single chip microprocessor and for modifying the control signals from said microprocessor to conform to the control signals of said memory system.
References Cited (Backward Citations)
US3703707A
Cited
US5179667A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |