US5537581A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor with a core that operates at multiple frequencies
Assignee: Intel Corp
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Filing: 1993-03-24
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Granted: 1996-07-16
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Expires: 2013-03-24
Abstract
Abstract A microprocessor that operates at the speed of the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals to clock the operations within the microprocessor and bus clock signals to clock data transfer operations between the microprocessor and the bus.
Inventors
- 👤 James W. Conary
- 👤 Robert R. Beutler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:30
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F13/00; G06F13/38; G06F1/00; G06F1/04; G06F1/08; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3237; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835; G06F12/0891; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30083; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
146 words
A microprocessor device formed in a single integrated circuit chip, comprising: a CPU core that executes instructions in response to a core clock signal; a bus interface unit that transfers data between external terminals of the microprocessor device and said CPU core, the bus interface unit transferring data in accordance with a bus clock signal; a clock generator that receives a signal of a first frequency from a source external to the microprocessor and generates said core clock signal from said signal of said first frequency; a clock control coupled to said clock generator and having a first condition and a second condition, said first condition causing said clock generator to produce said core clock signal at a second frequency which is a multiple of said first frequency, and said second condition causing said clock generator to produce said core clock signal at said first frequency.
Claim 2
Dependent Claim
146 words
A microprocessor device formed in a single integrated circuit chip, comprising: a CPU core that executes instructions in response to a core clock signal; a bus interface unit that transfers data between external terminals of the microprocessor device and said CPU core, the bus interface unit transferring data in accordance with a bus clock signal; a clock generator that receives a signal of a first frequency from a source external to the microprocessor and generates said core clock signal from said signal of said first frequency; a clock control coupled to said clock generator and having a first condition and a second condition, said first condition causing said clock generator to produce said core clock signal at a second frequency which is a multiple of said first frequency, and said second condition causing said clock generator to produce said core clock signal at said first frequency.
Claim 3
Dependent Claim
51 words
The microprocessor device according to claim 1 wherein said clock control includes at least one external control pin, said at least one external control pin enabling receipt of an input from a source external to the microprocessor device to place the clock control into the first condition or the second condition.
Claim 4
Dependent Claim
37 words
The microprocessor device according to claim 1 wherein said clock control includes at least one bonding pad on said integrated circuit chip to permanently select the first condition or the second condition via at least one pin.
Claim 5
Dependent Claim
31 words
The microprocessor device according to claim 3 wherein the microprocessor device is housed in a package, and said at least one bonding pad is coupled to the package with wire bonding.
Claim 6
Dependent Claim
31 words
The microprocessor device according to claim 3 wherein the microprocessor device is housed in a package, and said at least one bonding pad is coupled to the package by tape-automated bonding.
Claim 7
Dependent Claim
43 words
The microprocessor device according to claim 1 wherein said clock control includes an metal pattern on a face of said integrated circuit chip wired in a first position to select said first condition and in a second position to select said second condition.
Claim 8
Dependent Claim
16 words
The microprocessor device according to claim 1 wherein the second frequency is double the first frequency.
Claim 9
Independent Claim
312 words
A method of making microprocessors, each of said microprocessor being in the form of a single integrated circuit chip with interconnections on a face of said integrated circuit chip, said microprocessors including a first plurality of microprocessors with a first plurality of interconnections on said face of a first plurality of said integrated circuit chips and a second plurality of microprocessors with a second plurality of interconnections on said face of a second, different plurality of said integrated circuit chips, said method comprising the steps of: forming a number of said integrated circuit chips, each of said integrated circuit chips having: a CPU core area containing a core that executes instructions, the core operating at a clock speed responsive to a core clock signal applied to said core; a bus control area containing a bus interface unit that transfers data between external terminals of said integrated circuit chip and said core, the bus interface unit operating at a clock speed responsive to a bus clock signal applied to said bus control area; a clock generator area containing a clock generator operable to receive a signal of a first frequency and to generate said core clock signal; a clock control coupled to said clock generator and having a first condition and a second condition, said first condition causing said clock generator to produce said core clock signal at a second frequency which is a multiple of said first frequency, and said second condition causing said clock generator to produce said core clock signal at said first frequency; forming said first plurality of interconnections on said face of said first plurality of said integrated circuit chips to define said first condition of said clock control; and forming said second plurality of interconnections on said face of said second, different plurality of said integrated circuit chips to define said second condition of said clock control.
Claim 10
Independent Claim
312 words
A method of making microprocessors, each of said microprocessor being in the form of a single integrated circuit chip with interconnections on a face of said integrated circuit chip, said microprocessors including a first plurality of microprocessors with a first plurality of interconnections on said face of a first plurality of said integrated circuit chips and a second plurality of microprocessors with a second plurality of interconnections on said face of a second, different plurality of said integrated circuit chips, said method comprising the steps of: forming a number of said integrated circuit chips, each of said integrated circuit chips having: a CPU core area containing a core that executes instructions, the core operating at a clock speed responsive to a core clock signal applied to said core; a bus control area containing a bus interface unit that transfers data between external terminals of said integrated circuit chip and said core, the bus interface unit operating at a clock speed responsive to a bus clock signal applied to said bus control area; a clock generator area containing a clock generator operable to receive a signal of a first frequency and to generate said core clock signal; a clock control coupled to said clock generator and having a first condition and a second condition, said first condition causing said clock generator to produce said core clock signal at a second frequency which is a multiple of said first frequency, and said second condition causing said clock generator to produce said core clock signal at said first frequency; forming said first plurality of interconnections on said face of said first plurality of said integrated circuit chips to define said first condition of said clock control; and forming said second plurality of interconnections on said face of said second, different plurality of said integrated circuit chips to define said second condition of said clock control.
Claim 11
Dependent Claim
49 words
The method according to claim 8 wherein said step of forming said number of integrated circuit chips includes forming said integrated circuit chips on wafers having a large number of integrated circuit chips, then after said steps of forming said interconnections, dividing said wafers into separate integrated circuit chips.
Claim 12
Dependent Claim
173 words
A microprocessor device formed in a single integrated circuit chip for use in a computer system, comprising: a CPU core that executes instructions in response to a core clock signal; a bus interface unit that transfers data between external terminals of the microprocessor device and said CPU core, the bus interface unit transferring data in accordance with a bus clock signal; a clock generator that receives a signal of a first frequency from a source external to the microprocessor and generates said core clock signal from said signal of said first frequency and said bus clock signal; a clock control coupled to said clock generator and having a first condition and a second condition, said first condition causing said clock generator to produce said core clock signal at a second frequency which is a multiple of said first frequency, and said second condition causing said clock generator to produce said core clock signal at said first frequency, wherein the first and second conditions are derived from a storage area in the computer system.
Claim 13
Dependent Claim
173 words
A microprocessor device formed in a single integrated circuit chip for use in a computer system, comprising: a CPU core that executes instructions in response to a core clock signal; a bus interface unit that transfers data between external terminals of the microprocessor device and said CPU core, the bus interface unit transferring data in accordance with a bus clock signal; a clock generator that receives a signal of a first frequency from a source external to the microprocessor and generates said core clock signal from said signal of said first frequency and said bus clock signal; a clock control coupled to said clock generator and having a first condition and a second condition, said first condition causing said clock generator to produce said core clock signal at a second frequency which is a multiple of said first frequency, and said second condition causing said clock generator to produce said core clock signal at said first frequency, wherein the first and second conditions are derived from a storage area in the computer system.
Claim 14
Dependent Claim
18 words
The microprocessor device according to claim 10 wherein the storage area is external to the integrated circuit chip.
Claim 15
Dependent Claim
17 words
The microprocessor device according to claim 10 wherein the storage area is on the integrated circuit chip.
Claim 16
Dependent Claim
15 words
The microprocessor device according to claim 10 wherein the storage area comprises a control register.
Claim 17
Dependent Claim
51 words
The microprocessor device according to claim 13 wherein the control register comprises a control bit, wherein the first condition is generated in response to the control bit being in a first logic state and the second condition is generated in response to the control bit being in a second logic state.
Claim 18
Dependent Claim
25 words
The microprocessor device according to claim 10 wherein the storage area is programmed, such that either the first condition or the second condition is generated.
Claim 19
Dependent Claim
46 words
The microprocessor device according to claim 10 wherein the first or second condition is generated during a reset of the microprocessor device, such that the clock control causes the clock generator to produce said core clock signal at either the second frequency or the first frequency.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |