EP0366326A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Apparatus for low skew system clock distribution and generation of 2x frequency clocks
Assignee: HP Inc
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Filing: 1989-10-16
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Granted: —
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Expires: 2009-10-16
Abstract
Abstract A phase-locked loop clock regeneration circuit which removes board-to-board system skew and further provides a second order loop to adjust the cycle-to-cycle symmetry of a 2X frequency clock.
Inventors
- 👤 Scott Markinson
- 👤 Michael Shuster
- 👤 Thomas Hogan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 15:53
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F1/06; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/16
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
99 words
Apparatus for a generation of a synchronized clock signal comprising: clock signal distribution means providing a plurality of clock output signals having a selected phase relationship therebetween and having a delay from said reference clock signal; and means for providing a reference clock signal phase Lock Loop means receiving said reference clock signal and a selected one of said distributors means output signal providing an out put signal to said clock distribution means for maintaining a phase relationship between each said distribution means output signal and said reference clock signal, wherein said apparatus compensates for the distribution means delay.
Claim 2
Dependent Claim
99 words
Apparatus for a generation of a synchronized clock signal comprising: clock signal distribution means providing a plurality of clock output signals having a selected phase relationship therebetween and having a delay from said reference clock signal; and means for providing a reference clock signal phase Lock Loop means receiving said reference clock signal and a selected one of said distributors means output signal providing an out put signal to said clock distribution means for maintaining a phase relationship between each said distribution means output signal and said reference clock signal, wherein said apparatus compensates for the distribution means delay.
Claim 3
Dependent Claim
31 words
The apparatus of claim 1, wherein said selected one of said distribution means output signals has a delay from said received reference signal different from other said distribution means output signals.
Claim 4
Dependent Claim
35 words
The apparatus of claim 1, further including frequency multiplier means receiving said phase lock loop output signal and providing an output signal at a frequency being a multiple of said phase lock loop output signal.
Claim 5
Dependent Claim
49 words
The apparatus of claim 3, wherein said frequency multiplier means output signals comprises plural portions each having a specified duty cycle relative to said output signal of said phase lock loop, said apparatus further including duty cycle control means for providing a selected duty cycle of each said portion.
Claim 6
Dependent Claim
42 words
The apparatus of claim 4, wherein said frequency multiplier means output signal comprises two portions corresponding to each portion of said phase lock loop output signal, and said duty cycle means provides a substantially equal duty cycle of each said two positions.
Claim 7
Dependent Claim
54 words
Apparatus for providing a frequency multiplier clock means for providing a reference clock signals comprising multiplier means for providing an output signal having a plurality portions for each corresponding portion of said reference clock frequency; duty cycle adjust means for selectively adjusting the duty cycle of each said portion of said multiplier output signal.
Claim 8
Dependent Claim
54 words
Apparatus for providing a frequency multiplier clock means for providing a reference clock signals comprising multiplier means for providing an output signal having a plurality portions for each corresponding portion of said reference clock frequency; duty cycle adjust means for selectively adjusting the duty cycle of each said portion of said multiplier output signal.
Claim 9
Dependent Claim
36 words
The apparatus of claim 6, wherein said multiplier means output comprising two portions for each reference clock signal portion, and said duty cycle means maintains a substantially equal duty cycle between said first and second portions.
References Cited (Backward Citations)
No citation records indexed.
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