US5416367A
Expired / Lapsed
US
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Programmable application specific integrated circuit and logic cell therefor
Assignee: QuickLogic Corp
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Filing: 1994-01-31
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Granted: 1995-05-16
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Expires: 2014-01-31
Abstract
Abstract A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.
Inventors
- 👤 Andrew K. Chan
- 👤 John M. Birkner
- 👤 Hua T. Chua
- 👤 William D. Cox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; H03K19/177; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/17736; H03K19/1778; H03K19/17784; H03K19/17792
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
390 words
A logic module having a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, a tenth, an eleventh, a twelfth, and a thirteenth input terminal, said logic module also having a first and a second output terminal, said logic module comprising: a first logic gate having a first data input lead coupled to said first input terminal, a second data input lead coupled to said second input terminal, and an output lead coupled to said first output terminal; a second logic gate having a first data input lead coupled to said third input terminal, a second data input lead coupled to said fourth input terminal, and an output lead; a third logic gate having a first data input lead coupled to said fifth input terminal, a second data input lead coupled to said sixth input terminal, and an output lead; a first multiplexer having a first data input lead coupled to said output lead of said second logic gate, a second data input lead coupled to said output lead of said third logic gate, a select input lead coupled to said seventh input terminal, and an output lead; a fourth logic gate having a first data input lead coupled to said eighth input terminal, a second data input lead coupled to said ninth input terminal, and an output lead; a fifth logic gate having a first data input lead coupled to said tenth input terminal, a second data input lead coupled to said eleventh input terminal, and an output lead; a second multiplexer having a first data input lead coupled to said output lead of said fourth logic gate, a second data input lead coupled to said output lead of said fifth logic gate, a select input lead coupled to said seventh input terminal, and an output lead; a third multiplexer having a first data input lead coupled to said output lead of said first multiplexer, a second data input lead coupled to said output lead of said second multiplexer, a select input lead coupled to said twelfth input terminal, and an output lead; and a flip-flop having a clock input lead coupled to said thirteenth input terminal, a data input lead coupled to said output lead of said third multiplexer, and a data output lead coupled to said second output terminal.
Claim 2
Dependent Claim
390 words
A logic module having a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, a tenth, an eleventh, a twelfth, and a thirteenth input terminal, said logic module also having a first and a second output terminal, said logic module comprising: a first logic gate having a first data input lead coupled to said first input terminal, a second data input lead coupled to said second input terminal, and an output lead coupled to said first output terminal; a second logic gate having a first data input lead coupled to said third input terminal, a second data input lead coupled to said fourth input terminal, and an output lead; a third logic gate having a first data input lead coupled to said fifth input terminal, a second data input lead coupled to said sixth input terminal, and an output lead; a first multiplexer having a first data input lead coupled to said output lead of said second logic gate, a second data input lead coupled to said output lead of said third logic gate, a select input lead coupled to said seventh input terminal, and an output lead; a fourth logic gate having a first data input lead coupled to said eighth input terminal, a second data input lead coupled to said ninth input terminal, and an output lead; a fifth logic gate having a first data input lead coupled to said tenth input terminal, a second data input lead coupled to said eleventh input terminal, and an output lead; a second multiplexer having a first data input lead coupled to said output lead of said fourth logic gate, a second data input lead coupled to said output lead of said fifth logic gate, a select input lead coupled to said seventh input terminal, and an output lead; a third multiplexer having a first data input lead coupled to said output lead of said first multiplexer, a second data input lead coupled to said output lead of said second multiplexer, a select input lead coupled to said twelfth input terminal, and an output lead; and a flip-flop having a clock input lead coupled to said thirteenth input terminal, a data input lead coupled to said output lead of said third multiplexer, and a data output lead coupled to said second output terminal.
Claim 3
Dependent Claim
37 words
The logic module of claim 1, wherein said logic module consists essentially of no digital logic elements other than said first, second, third, fourth and fifth logic gates, said first, second and third multiplexers, and said flip-flop.
Claim 4
Dependent Claim
25 words
The logic module of claim 1, wherein said logic module also has a third output terminal coupled to said output lead of said third multiplexer.
Claim 5
Dependent Claim
25 words
The logic module of claim 3, wherein said logic module also has a fourth output terminal coupled to said output lead of said second multiplexer.
Claim 6
Dependent Claim
145 words
The logic module of claim 1, wherein said logic module also has a fourteenth, a fifteenth, a sixteenth, and a seventeenth input terminal, and wherein said first logic gate comprises: a NOR gate having a first input lead coupled to said second input terminal, a second input lead coupled to said fifteenth input terminal, a third input lead coupled to said seventeenth input terminal, and an output lead; a NAND gate having a first input lead coupled to said first input terminal, a second input lead coupled to said fourteenth input terminal, a third input lead coupled to said sixteenth input terminal, a fourth input lead coupled to said output lead of said NOR gate, and an output lead; and an inverter having an input lead coupled to said output lead of said NAND gate, and an output lead coupled to said first output terminal.
Claim 7
Dependent Claim
230 words
A logic module having a first and a second input terminal and also having a first and a second output terminal, said logic module comprising: a first multiplexer having a first data input lead, a second data input lead, a select input lead coupled to said first input terminal, and an output lead; a second multiplexer having a first data input lead, a second data input lead, a select input lead coupled to said first input terminal, and an output lead; a third multiplexer having a first data input lead coupled to said output lead of said first multiplexer, a second data input lead coupled to said output lead of said second multiplexer, a select input lead coupled to said second input terminal, and an output lead; a flip-flop having a data input lead coupled to said output lead of said third multiplexer and also having an output lead coupled to said first output terminal; and a first logic gate having an output lead coupled to said second output terminal, said output lead of said first logic gate not being coupled to a select input lead of any one of said first multiplexer, said second multiplexer, and said third multiplexer, said output lead of said first logic gate not being coupled to a data input lead of any one of said first multiplexer, said second multiplexer, and said third multiplexer.
Claim 8
Dependent Claim
230 words
A logic module having a first and a second input terminal and also having a first and a second output terminal, said logic module comprising: a first multiplexer having a first data input lead, a second data input lead, a select input lead coupled to said first input terminal, and an output lead; a second multiplexer having a first data input lead, a second data input lead, a select input lead coupled to said first input terminal, and an output lead; a third multiplexer having a first data input lead coupled to said output lead of said first multiplexer, a second data input lead coupled to said output lead of said second multiplexer, a select input lead coupled to said second input terminal, and an output lead; a flip-flop having a data input lead coupled to said output lead of said third multiplexer and also having an output lead coupled to said first output terminal; and a first logic gate having an output lead coupled to said second output terminal, said output lead of said first logic gate not being coupled to a select input lead of any one of said first multiplexer, said second multiplexer, and said third multiplexer, said output lead of said first logic gate not being coupled to a data input lead of any one of said first multiplexer, said second multiplexer, and said third multiplexer.
Claim 9
Dependent Claim
93 words
The logic module of claim 6 also including: a second logic gate coupled to said first data input lead of said first multiplexer, a third logic gate coupled to said second data input lead of said first multiplexer, a fourth logic gate coupled to said first data input lead of said second multiplexer, and a fifth logic gate coupled to said second data input lead of said second multiplexer, wherein said logic module consists essentially of: said first, second, third, fourth, and fifth gates, said first, second and third multiplexers, and said flip-flop.
Claim 10
Dependent Claim
30 words
The logic module of claim 7, wherein each of said second through fifth gates is a two-input AND gate having both an inverting input lead and a non-inverting input lead.
Claim 11
Dependent Claim
64 words
The logic module of claim 6, wherein said first logic gate comprises a first single logic level gate and a second single logic level gate, said first single logic level gate having input leads coupled to input terminals of said logic module, said first single logic level gate having an output lead coupled to an input lead of said second single logic level gate.
Claim 12
Dependent Claim
29 words
The logic module of claim 9, wherein said first single logic level gate is a NOR gate and wherein said second single logic level gate comprises a NAND gate.
Claim 13
Dependent Claim
39 words
The logic module of claim 6, wherein said data output lead of said third multiplexer is coupled to a third output terminal and wherein said data output lead of said second multiplexer is coupled to a fourth output terminal.
Claim 14
Dependent Claim
49 words
The logic module of claim 6, wherein said logic module also has a third and a fourth input terminal, and wherein said flip-flop has a set input lead coupled to said third input terminal, and wherein said flip-flop has a reset input lead coupled to said fourth input terminal.
Claim 15
Dependent Claim
89 words
The logic module of claim 6 also having a third output terminal and also including: a second logic gate having an output lead coupled to said third output terminal, said output lead of said second logic gate not being coupled to a select input lead of any one of said first multiplexer, said second multiplexer, and said third multiplexer, said output lead of said second logic gate not being coupled to a data input lead of any one of said first multiplexer, said second multiplexer, and said third multiplexer.
Claim 16
Dependent Claim
41 words
The logic module of claim 13, input leads of said first logic gate being directly connected to input terminals of said logic module, input leads of said second logic gate being directly connected to other input terminals of said logic module.
Claim 17
Dependent Claim
24 words
The logic module of claim 14, wherein said first logic gate and said second logic gate each has both inverting and non-inverting input leads.
References Cited (Backward Citations)
US3619583A
Cited
US4453096A
Cited
US4354266A
Cited
US4491839A
Cited
US4616358A
Cited
US4551634A
Cited
US4787064A
Cited
US4684829A
Cited
US4577124A
Cited
US4558236A
Cited
US4870302A
Cited
US4852021A
Cited
US4642487A
Cited
US4825105A
Cited
US4620117A
Cited
US4706216A
Cited
US4758985A
Cited
US4933577A
Cited
US4754456A
Cited
US4764893A
Cited
US4910466A
Cited
US4710649A
Cited
US4789951A
Cited
US4910417A
Cited
US4873459A
Cited
US4873459B1
Cited
US5019736A
Cited
US4786904A
Cited
US5068603A
Cited
US4963770A
Cited
US5045714A
Cited
US4912339A
Cited
US4940908A
Cited
US5015883A
Cited
US5055718A
Cited
US5280202A
Cited
US5338983A
Cited
US5349250A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-15 | 1998-11-14 | 1999-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-15 | 2002-11-14 | 2003-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-15 | 2006-11-14 | 2007-05-16 | $7700.00 | Window Closed / Lapsed |